This training course introduces the Verilog-AMS modelling language and the ways that Verilog-AMS can be used in both Analogue and Mixed-Signal design flows. The practical sessions of this course will use the Siemens mixed-signal solution with Symphony, part of Solido™ Simulation Suite.

The course will introduce the core syntax and main features of the Verilog-AMS language, including a review of standard Verilog syntax, and a more in-depth look at both the Verilog-A and Verilog-AMS language feature sets. The course will introduce the different modelling styles and approaches, as well as demonstrating their typical use cases. After attending this course, attendees will be able to incorporate and apply what they have learnt into their own design flows.

The course schedule:

• Day 1
  • Introduction to the mixed-signal simulator
  • Modelling styles and approaches
  • Fundamentals of Verilog languages
  • Fundamentals of Verilog-A syntax

• Day 2
  • Mixed Signal Features of Verilog-AMS
  • Connect Modules and Interface Elements
  Analogue System Tasks/li>

• Day 3
  • Verilog-AMS features for Testbenches
  • Model Continuity and Convergence
  • Common Problems

Theory and concepts are introduced in lectures and practically illustrated in comprehensive lab exercises utilising the Siemens mixed-signal solution with Symphony, part of Solido™ Simulation Suite. Experience with the Siemens suite of EDA tools in not required for this course.

This course will cover the fundamentals of standard Verilog; however, this is not comprehensive. Therefore, familiarity with Verilog or SystemVerilog is recommended but not required.

All practical exercises will use Linux workstations, thus previous experience of using UNIX/Linux systems is advantageous.