EASE is a graphical HDL design entry tool. Designs are created using a mix of graphics/text and then automatically generates optimized HDL code in VHDL or Verilog. EASE comprises of several modules:

  • Block diagram editor easily allows the designer to decompose a system into functional blocks
  • State diagram editor for graphical creation of synchronous or asynchronous Moore, Mealy and mixed state machines
  • Truth table editor
  • HDL language editor
  • Linter
  • Design browser for an overview of the complete design including used libraries, packages and configurations

Additional information can be found in the following HDL Works EASE Datasheet

Ease HDL

HDL Companion

HDL Companion is an HDL analysis and navigation environment. HDL Companion offers a complete overview of your design, from high level structure to the details in the source code. Features include signal tracing, a Tcl interpreter, revision control and a language sensitive text editor.

HDL Companion accepts VHDL, Verilog and mixed language source code and automatically extracts numerous design details from the code. Incomplete designs or and uncompiled code are accepted. The user interface provides an overview and navigation of all objects and files and it shows the complete design hierarchy

Additional information can be found in the following HDL Works HDL Companion Datasheet

Ease HDL

Supported Machine Types

WINDOWS (64 bit): Windows 7/8.1/10

LINUX (64 bit): Likely to be compatible with most recent distribtions. Tested with RHEL6 and 7.

The tools are protected by means of a floating FlexLM license.