Xilinx, now part of AMD, is a provider of FPGA (Field Programable Gate Arrays) devices. They provide a comprehensive suite of development tools for FPGA design and development. They have a plethora of multi-node FPGAs with special graded options for automotive, defence and space applications. Xilinx’s current multi-node portfolio
Vivado ML is an HDL to FPGA implementation tool that has replaced Vivado HLx edition since version 2021.1. Vivado ML has the same functionality as Vivado HLx enterprise edition (see below) with improved performance via machine learning algorithms. Vivado ML includes Model Composer and Vitis HLS as standard.
Vivado ML provides support for all HLx devices along with:
Vivado HLx Edition (succeeded by ML edition) integrates Vivado HLS as part of the suite allowing for C/C++ languages to be utilised for both HDL design and verification. Vivado supports the 7 Series and zynq Xilinx devices (Artix, Kintex, Virtex, Spartan) with options for Ultrascale, low voltage and MPSoCs also available.
Last version of Vivado HLx (2020.3) comes with versal platforms, Pentalinux, Block Design container, Dynamic Function eXchange, Vitis HLS (with an add-on for MATLAB and Simulink).
The current and previous Vivado documentation can be found here
Xilinx’s high level synthesis tool allows for software to Hardware conversion, testing and implementation. Vivado HLS has been developed for use with C, C++ and SystemC, allowing for these languages to be utilised for both HDL design and verification.
Please be aware, SystemC is no longer supported past version 2019.x.
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