Licenses for options are generated on the same servers (with the same number of seats as the main package). It is not possible to give any separate licensing information. Please use the Cadence Optional Packages Order Form to request the options. Supplementary maintenance fees for the options are clarified on the order form.
The JasperGold formal verification platform is comprised of a range of formal verification apps which incorporate machine learning to improve verification productivity.
The Europractice Optional Package includes:
JasperGold Formal Verification Platform Package 2024 | Release Name | Key Tools | Supported Platforms * |
---|---|---|---|
Linux (lnx86) | |||
Formal Verification | JasperGold Formal Verification Platform JASPER 2023.09 |
- Behavioural Property Synthesis - Formal Property Verifier - Superlint verification - Clock Domain Crossing Verification - Sequential Equivalence Checking - Connectivity (analysis?) - Control and Status register - X Propagation - Unreachability analysis - Coverage - Security path verification - Jasper C2RTL |
RHEL 7, 8 |
The 3DIC option provides tools to enable advanced 2.5D,3D, chiplet and hetereogenous IC system design. This includes Integrity, a tool focused on 3DIC designs helping ease the process of combing multiple chips together in heterogeneously integrated designs. Integrity includes many system planning, floorplanning, interposer design, IO planning, system analysis and system verification features to expedite the design flow of this type of design. The Voltus 3D option is also included, enabling power integrity analysis for 3DIC designs.
The Europractice Optional Package includes:
3DIC Package 2024 | Release Name | Key Tools | Supported Platforms * |
---|---|---|---|
Linux (lnx86) | |||
Integrity 3DIC Platform | DDIEXPORT 22.1 |
- 3DIC System planning and implementation - Inteposer planning - 3DIC stack design - IO, Bump, and TSV planning and optimisation - 3DIC system analysis and verification - Co-design with Allegro and Virtuoso |
RHEL 7, 8 |
Silicon Signoff & Verification | SSV 22.1 | - Voltus 3DIC Power Integrity Option | RHEL 7, 8 |
With Stratus HLS, you can quickly design and verify high-quality RTL implementations from abstract IEEE 1666 synthesisable SystemC, C, or C++ models. The models can be easily created using the Stratus integrated design environment (IDE).
With Stratus HLS, SystemC models can be retargeted to new technology platforms and reused more easily than traditional hand-coded RTL.
The Europractice Optional Package includes:
Stratus High Level Synthesis Package 2024/th> | Release Name | Key Tools | Supported Platforms * |
---|---|---|---|
Linux (lnx86) | |||
High Level Synthesis | Stratus HLS STRATUS 23.01 |
- Quickly create high-quality RTL from abstract SystemC models - Create truly reusable designs by focusing on function instead of implementation Explore area, performance, and power trade-offs within the Stratus HLS environment - Improve design and verification time |
RHEL 7, 8 |
The Cadence® Legato™ Reliability Solution provides analogue designers with the tools they need to manage their design’s relia bility throughout the product lifecycle. Responding to the challenges of designing for mission-critical applications such as automotive, aerospace, and medical design, the Legato Reliability Solution includes new technology to simulate the manufacturing test’s ability to identify and eliminate de fective parts, the effect of temperature on circuit electrical performance, and changes in devices over time including the effects of temperature and p rocess variation on aging.
The Europractice Optional Package includes:
Legato Reliability solution Package 2024 | Release Name | Key Tools | Supported Platforms * |
---|---|---|---|
Linux (lnx86) | |||
Analogue/Custom reliability analysis | Spectre® Simulation Platform SPECTRE 23.1 |
- Analyses test coverage of manufacturing test using analogue defect simulation - Advanced aging analysis for better prediction of device operating lifetime - Performs dynamic electrothermal simulation of design to prevent thermal overstress during operation - Analog defect simulation is integrated into the Spectre® AMS Designer to enable simulation of mixed-signal designs - Based on the Virtuoso® custom IC design platform and Spectre Accelerated Parallel Simulator (APS) for fast, easy adoption |
RHEL 7, 8, 9 |
The SiP Option additionally provides Digital and RF SiP design capabilities, streamlining the integration of multiple chips (into a die stack or single substrate). It includes tools for architecting SiP systems by capturing and exploring top-level SiP connectivity, IC/package IO planning and optimisation for 3D die stack creation, 3D die stack viewing, DRC, bondability verification, and cross-die RF SiP simulation.
The Europractice Optional Package includes:
System in Package (SiP) 2024 | Release Name | Key Tools | Supported Platforms * | |
---|---|---|---|---|
Linux (lnx86) | Windows (10, 11 Server 2012, Server 2016) |
|||
Power Integrity | Allegro® Sigrity™ SIGRITY 2023.1 |
- Voltus IC Power integrity solution | RHEL 7.4, 8 | Yes |
Relational Rules | System, Package & Board SPB 23.1 |
- Allegro relational rules developer and checker | RHEL 7, 8, 9 | Yes |
System Design Platform | Virtuoso Studio® Custom Design Platform IC 23.1 |
- Virtuoso Studio System Design Platform | RHEL 7, 8, 9 | No |
This Europractice option includes the Advanced Node version of the Virtuoso and Innovus platforms. This additional functionality is necessary for custom design at 20nm and below or digital design at 10nm and below. It is complemented by the Quantus advanced node extraction capabilities found in the IC Package. The advanced node capabilities of this version of Virtuoso are also required for some 28nm and 22nm FDSOI design kits.
The Europractice Optional Package includes:
IC Advanced Node Package 2024 | Release Name | Key Tools | Supported Platforms * |
---|---|---|---|
Linux (lnx86) | |||
Advanced node Analogue/Full Custom Design Tools | Virtuoso Studio® Advanced Node IC 23.1 |
- Advanced Node framework - Photonics option - RF option - Layout Suite MXL |
RHEL 7, 8, 9 |
Digital Implementation Tools | Innovus™ Implementation System DDIEXPORT 22.1 |
- Place & Route / Digital Physical Implementation 10nm and below | RHEL 7, 8 |
Physical Verification | Pegasus DFM PEGASUSDFM 23.1 |
- Lithography analyser | RHEL 7, 8 |
Pegasus Verification System PEGASUS 23.1 |
- Integrated Physical Verification System Advanced Analysis | RHEL 7, 8, 9 |
The Virtual System Platform Option includes Helium Virtual and Hybrid studio which allows the development of Virtual Platforms. Virtual Platforms enable pre-RTL software development, functional verification, and system analysis and optimization before committing to hardware micro-architecture. VSP automates the process of creating a virtual prototype, debugging software with a virtual prototype, and deploying the virtual prototype to the software team.
Virtual Platforms can also be used after RTL/Silicon is available. The Virtual Platform allows greater visibility than a hard ware prototype, allowing better debug and verification of internal blocks and signals, and offers much greater performance than RTL simulation, allowing interactive debugging of software applications running on t he Virtual platform.
The Europractice Optional Package includes:
Virtual System Platform (VSP) Package 2024 | Release Name | Key Tools | Supported Platforms * |
---|---|---|---|
Linux (lnx86) | |||
Hardware/Software co-verification and debug | Cadence® Helium™ Virtual and Hybrid Studio HELIUM 22.12 |
- Creation of virtual and hybrid platforms - Unified debug from virtual to hybrid to RTL - Native integration with Xcelium |
RHEL 7.4, 7.6, 7.8, 7.9, 8.1, 8.4 |
VSP requires 3rd party processor models from Imperas (OVP models - support for ARM, ARC, MIPS, etc.). Imperas models are included in the VSP installation, however, a license for Imperas must be obtained separately before VSP can be used. Licenses for Imperas are available through EUROPRACTICE.
For further information on processor models, and how to order, please see our Imperas Pages
Liberate AMS enables the timing characterisation of mixed signal blocks to be used in a digital-centric mixed signal flow. Liberate AMS is available to
Europractice users on request and at Cadence's approval.
The well established tools Liberate and Liberate LV for library characterisation and validation are available as part of the core IC pacakge.
The Europractice Optional Package includes:
Virtuoso Liberate AMS Mixed Signal Package 2024 | Release Name | Key Tools | Supported Platforms * |
---|---|---|---|
Linux (lnx86) | |||
Library characterisation and validation | Virtuoso Library Characterisation LIBERATE 23.1 |
- Liberate Variety statistical characterisation - Liberate MX Memory characterisation - Liberate AMS Mixed-Signal characterisation |
RHEL 7, 8, 9 |
All potential users interested in using Liberate AMS should contact the Microelectronics Support Centre via MicroelectronicsCentre@stfc.ac.uk for further information.