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Course
Title: Hands-on PDK training on IC design and simulation of 2D materials-based photonic devices organized by the 2D Pilot Line - in-person training
Start Date: 02-Nov-2026
End Date: 04-Nov-2026
Time: 09:30 to 17:30 each day (local time)
Training Hours: 21 hours
Location: imec, Leuven, Belgium
Presenters: Experts from 2D Pilot Line partners (AMO GmbH, Graphenea, IHP, VTT)
Cost: 300.00 EURO
Closing Date: Registration closes 23-Oct-2026 or earlier when places are filled.
Notes:

It is possible to attend just the morning of day 1 (introductory seminars) please book here

Overview:

Learn how to design photonic devices with the 2D Pilot Line! This is an intensive 3-day hands-on training on design practices for 2D material-based photonic integrated circuits (PICs) on KLayout. This course will guide participants from fundamental concepts and design tools to more advanced implementations and exercises for photonic device architectures using our 2D-PL partners’ four diverse PDKs. The event will be carried out by expert designers involved in the EU-funded project 2D-PL, a part of the Graphene Flagship initiative.

Details:

The training will begin with a kick-off seminar, available for both in-person and remote attendees. This introductory session will be led by the 2D-PL host partners’ representatives, with contributions of invited speakers from the broader photonics community. The talks will shed light on the developments achieved so far in the integration flows of the 2D material-based device fabrication, which enables further maturation of the Process Design Kits.


After the break, the first day will continue with a session co-hosted by AMO GmbH and Graphenea Semiconductors which will cover the basic and fundamental concepts of KLayout. Expert trainers will guide participants through best practices in layout design, design rule compliance, and preparation of tape-out files for multi-project wafer (MPW) run fabrication. The Graphene Device PDK will allow attendees to move confidently from design (including layout creation and design rule checks (DRCs)) to fabrication, regardless of their familiarity with the software. The class will thus lay the groundwork for the more advanced VTT and IHP classes over the following two days.


Day 2: The VTT class will begin with a description of VTT’s silicon nitride (SiN) photonic platform, followed by a deeper look into the passives and active graphene components available in the process design kit (PDK) as well as its working principle. Background on the provided dimensions and earlier simulations is also provided along with design rule checks (DRC). A guided design demonstration builds a Mach-Zehnder interferometer (MZI) with selectable splitter options, after which an active photonic component, such as graphene modulator, is integrated into one branch. Circuit-performance simulations based on experimental data is included. The session closes with key conclusions and quick introduction to VTT’s upcoming MPW run.

The practical session will include:

  • Introduction to VTT, the platform and components
  • PDK details
  • Hands-on activity: Mach-Zehnder interferometer with variable splitter + active graphene component + simulation, DRC
  • Multi-project wafer run enablement

Day 3: The IHP course will introduce essential design flows and industry-standard tools for developing photonic integrated circuits (PICs) based on 2D materials. Participants will gain hands-on experience with Python, Nazca Design, and KLayout, using the IHP Graphene PDK as the primary design platform; thus, they will learn how to create connectivity-driven layouts for advanced photonic platforms while gaining practical experience with modern design workflows and techniques. By combining theoretical concepts with hands-on training, the course will equip attendees with the fundamental knowledge and practical skills to begin designing and implementing PICs using advanced 2D material technologies.

The practical session will include:

  • Introduction to the Graphene PDK
  • Design and layout of fundamental photonic building blocks
  • System-level layout implementation, including the integration of filler structures
  • Layout verification and validation using Design Rule Check (DRC) tools
Prerequisites:

Signature of NDAs and DKLAs required. You will need basic understanding of Python programming. Computers and software will be provided by IMEC.