This training course introduces the design flows and tools required to successfully analyse and implement analogue dominated mixed signal designs.

The aim of this course is to provide attendees with the design flow theory of analogue-centric mixed signal designs in typical CMOS processes. It will demonstrate the main steps for the Big-Analogue mixed signal design flow, including methodology, mixed signal simulation, physical integration of digital blocks, and full chip physical verification.

Theory and concepts are introduced in lectures and illustrated in comprehensive hands-on practical exercises utilising the Cadence tools from the EUROPRACTICE portfolio, and implementation of the design example within the UMC 65nm CMOS process.

The course schedule:

• Day 1
  • Big-A design methodology
  • Design considerations at the interface between digital and analogue blocks
  • Mixed signal simulation techniques

• Day 2
  • Behavioural system simulation
  • RTL Synthesis
  • Transistor level simulation with HDL integration
  • Physical implementation, including floorplanning and IO ring generation
  • Digital block implementation

• Day 3
  • Behavioural model update and validation
  • Post-layout simulation strategies
  • Chip assembly and data transfer between full custom and digital design platforms
  • Physical verification
  • Full chip sign off simulation

The focus of this course is on the key aspects of analogue-centric mixed signal design flows. Therefore, prior knowledge of the analogue design flows and tools is required. This course will provide introductions to digital design flows and tools, however basic knowledge of the digital design process would be useful. All practical exercises will use remotely-accessed Linux workstations so familiarity with a Linux environment is advantageous.