ASIC design introduction: From concept to silicon - A Europractice summer school
Start Date:
24-Aug-2026
End Date:
28-Aug-2026
Time:
Monday, Wednesday and Thursday 09:00 to 17:15. Tuesday 09:00 to 18:00 including networking drink. Friday 09:00 to 12:30 (local times)
Training Hours:
36 hours
Location:
imec, Leuven, Belgium
Presenters:
Experts from imec
Cost:
500.00 EURO
Closing Date:
Registration closes 17-Aug-2026 or earlier when places are filled.
Overview:
This Europractice summer school aims to provide an introduction to the ASIC design and development flow.
Details:
This summer school comprehensively covers multiple aspects and is broken up into various detailed topics including theory and concepts. Upon completion of this summer school, attendees will have a general understanding of the ASIC design flow.
The summer school schedule:
Day 1
Introduction to integrated circuits and fabrication of silicon chips. (Speaker: Giuseppe Fiorentino)
From ASIC to Product. Introduction to packaging and test: Relationship to design, technical and economic aspects. (Speaker: Hans Manhaeve)
Day 2
Digital Front-end design flow: basic steps (Speaker: Jorgo Tsouhlarakis)
Digital physical Implementation foundation flow and low power methodologies (Speaker: Amir Najafi)
Day 3
Analog Design: Introduction to analogue design flow. (Speaker: Florian De Roose)
Analog layout: Basics of analog physical layout, analog layout workflow, and failure mechanisms. (Speaker: Eduarda Silveira da Costa Losqui)
Day 4
IP fundamentals. Reasons for design reuse. Key legal and technical prospects and challenges. (Speaker: Paul Zuber)
Design for testability: The increasing cost of unfound defects and fault models' overview. (Speaker: Steven Dupont)
Day 5
Integrated circuit production test: role and aspects. (Speaker: Ugo Raia)
From classic to advanced packaging and chiplet integration. (Speaker: Sara louahdi)
Prerequisites:
This course is aimed at students and any other professional not directly working on microelectronics, but with a solid technical background and with a Bachelors or Masters degree (or with equivalent work experience) in Engineering Technology (e.g. engineers, physicists, chemists, etc).
Further details (PDF):
Ballot Information
We anticipate that this training will be oversubscribed. Please join the ballot and you will be contacted if you are successful in obtaining a place.
Waiting List Information
By submitting your details and joining the waiting list then you will be contacted should a place become free on this course. Joining the waiting list does not commit you to attend should a place become free, it just registers your interest in this course.