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Course
Title: Advanced PDK Workshop: NanoIC’s IGZO based eDRAM PDK - in-person training
Start Date: 26-May-2026
End Date: 26-May-2026
Time: 09:00 to 18:00 each day (local time)
Location: imec, Leuven, Belgium
Presenters: experts form imec
Cost: 100.00 EURO
Closing Date: Registration closes 11-May-2026 or earlier when places are filled.
Overview:

This workshop introduces the key foundations, materials, design principles, and potential applications behind NanoIC’s IGZO?based eDRAM PDK. Through the day, participants move from exploring the broader memory landscape to understanding the practical implementation of eDRAM architectures with IGZO-based technology, covering oxide?semiconductor fundamentals, device behaviour, reliability, and design?technology co?optimization.
Details:

This workshop will allow participants to gain a solid understanding of IGZO based eDRAM – from device physics to circuit level behaviour – and accelerate their learning curve for advanced memory technologies; translate theory into design insights, with practical guidance on how to apply the PDK in exploratory design and simulation flows to evaluate eDRAM architectures; prepare for advanced technology nodes, understanding the co optimization challenges and opportunities when integrating eDRAM into future chip platforms.


Agenda (technical presentations):

  • Memory landscape, system needs, emerging memories
  • Material deposition, morphology, and properties of IGZO
  • Transport, material selection rules, and doping for IGZO devices
  • Etch development for enabling semiconductor-based eDRAM
  • IGZO device fundamentals, optimization, and applications
  • IGZO integration and test vehicles for material screening learnings
  • Fundamental aspects of IGZO reliability
  • DTCO for 2ToC and 3T0C IGZO eDRAM memories
  • IGZO eDRAM PDK: what and how

Participants will have the opportunity to engage with imec experts developing the underlying technology and get answers to technical questions. An exclusive guided window tour of imec’s existing 300mm cleanroom is also included in the program.


The event is being organized as part of the (HORIZON-JU-Chips-2023-RIA-CPL-1; GA No. 101183277) initiative, which aims to support the European pilot line for research, innovation, and communication related to beyond 2nm leading edge System-on-Chip technology across the value chain.


This event directly precedes NanoIC’s Advanced Interconnect PDK training on May 27th, 2026 (for which practical details will be announced soon). We highly recommend combining both sessions to gain a broader understanding of interconnect technologies right after deep?diving into IGZO?based eDRAM.