This course takes participants through a full state of the art Digital IC implementation flow using Synopsys Fusion Compiler, covering the design flows required to successfully implement modern Digital IC designs, ready for manufacture.

The course starts with known good RTL code, and examines; synthesis, timing constraints, physical implementation (floorplanning, placement, CTS and Routing), design finishing, and signoff checks. Theory and concepts are covered in lectures with significant time given to detailed hands-on practical exercises using the Synopsys Fusion Compiler. The design flow is illustrated with an RTL SoC example design which is then taken through to layout (GDSII suitable for manufacture) in a 65nm CMOS process.

The course schedule:

• Day 1
  • Introduction and Digital Design Flows
  • IC Implementation Fundamentals
  • SDC Timing Constraints
  • Mapping, Optimisation & Design Analysis
  • Physical Synthesis

• Day 2
  • Power Optimisation
  • Scan Test Synthesis
  • Place and Route flow
  • Timing analysis
  • Design import and MCMM setup

• Day 3
  • Floorplanning
  • Power Planning
  • Early DRC and Rail Analysis
  • Placement and Optimization

• Day 4
  • Clock Tree Synthesis
  • Routing, Design Finishing & Verification
  • Introduction to Signoff
  • Data Export and Chip Finishing
  • Formal Equivalence Checking

• Day 5
  • Signoff RC Extraction
  • Signoff Static timing analysis with SI analysis
  • Gate level simulation
  • Signoff Power Analysis
  • Automatic Test Pattern Generation

The course is aimed at digital circuit designers who are either new to digital IC design or who are wishing to update their previous knowledge to the latest design flows and tool methodologies required to implement standard cell (semi-custom) Digital IC’s with a modern process. Basic understanding of the principles of digital circuits is required. Familiarity with UNIX environment would be helpful but not essential. The actual development of the design's RTL code is outside of the scope of this course.