Upon completion of this course, students will have a general  understanding of the ASIC design flow.

This course, through a series of lectures, aims to provide an introduction to the ASIC design and development flow . It comprehensively covers multiple aspects. This course is broken up to a various of detailed topics including theory and concepts.

The course schedule:

• Day 1 - 09:00 to 17:00 (Belgium local time)
  • An introduction to integrated circuits and the fabrication of silicon chips.
  • From ASIC to Product. Introduction to packaging and test: relationship to design, technical and economic aspects.
  • Clean Room tour visit.

• Day 2 - 09:00 to 16:00 (Belgium local time)
  • High level design flow : Basic steps to design a digital chip.
  • Low power methodologies.
  • From digital algebra to standard cells.
  • Digital physical Implementation foundation flow.
  • Low power methodologies.

• Day 3 - 09:00 to 16:00 (Belgium local time)
  • Analog Design: Introduction of analogue design flow.
  • Analog layout: Introduction to Analog Physical Layout,Analog Layout Workflow,Failure Mechanisms.

• Day 4 - 09:00 to 16:00 (Belgium local time)
  • Production test.
  • Classic packaging.
  • Chiplets: Because chips become too big.
  • Chiplets Heterogenous, Chiplets in automotive.

• Day 5 - 09:00 to 12:00 (Belgium local time)
  • Topics on IP, including reasons for IP and re-use, license models, and technical implications.
  • Design productivity vs chip size increase.
  • DFT: The increasing cost of unfound defects Fault models(SSA,Bridge,Transition), control and observe, why scan chain?

This course is aimed at students or young professionals with a Bachelors or Masters (or with equivalent work experience) in Engineering Technology (e.g. engineers, physicists, chemists or any other professional not directly working on microelectronics but with a solid technical background).