A key reason for the growing interest in RISC-V is the ability to customize or create RISC-V ISA and microarchitectural extensions to differentiate designs across application areas. This results in application-specific processors (ASIPs) that are composed of a RISC-V baseline architecture extended with specialized datapaths and storage structures. While supporting all standard RISC-V instructions, such architectures can also execute custom instructions that are encoded either in RISC-V's reserved opcode space or in additional parallel slots of an extended long instruction word.

Designing customized RISC-V architectures can be challenging, for multiple reasons. First, it is not obvious to decide which architecture extensions are best for the target application domain. Second, software engineers expect to get access to a high-quality software development kit (SDK) for the application-specific processor. Third, a reliable register-transfer level (RTL) implementation of the processor must become available for silicon implementation, with excellent power, performance, and area (PPA) characteristics.

This webinar will show how electronic design automation (EDA) tools can solve these challenges. Synopsys' ASIP Designer™ is a leading EDA tool to design and program application-specific processors. From a user-defined processor model, capturing the instruction-set and micro-architecture in the architecture description language nML, ASIP Designer automatically creates both a complete SDK with an efficient C/C++ compiler, and a synthesizable RTL implementation of the processor. With ASIP Designer’s unique Compiler-in-the-Loop™ and Synthesis-in-the-Loop™ methodologies, software compilation and RTL synthesis runs can be performed quickly and multiple times, to guide the architectural exploration.

ASIP Designer comes with example processor models representing RISC-V ISAs, which are freely available to ASIP Designer users. These processor models represent a baseline architecture to which users can add specialization using ASIP Designer's architectural exploration capabilities. This can range from scalar RISC-V architectures extended with highly specialized functional units, over very-long instruction word architectures with a RISC-V scalar issue slot combined with any number of parallel slots encoding custom instructions, to specialized architectures with wide SIMD (single-instruction, multiple-data) processing. Such processors have been deployed by ASIP Designer users in industrial designs for diverse markets including cloud & edge artificial intelligence, wireless, imaging, security, automotive, and supercomputing. ASIP Designer users own the RISC-V based processor intellectual property that they create using the tool.

This ASIP Designer design flow will be illustrated with a case study, showing the acceleration of a Post-Quantum Cryptography algorithm. Starting from an open-source implementation of the algorithm compiled and profiled on a RISC-V base model, architectural specializations are gradually added to the RISC-V base model.

Speaker: Dr Falco Munsche, Technical Product Manager·Synopsys

Falco is the Technical Product Manager for Synopsys' ASIP Designer tools. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare, and as a Design Consultant for Synopsys. He holds a Ph.D. (2002) and Dipl-Ing. Degree (1995) in Electrical Engineering from RWTH Aachen University.