This is a private course and attendance is strictly by invitation only. If you have not received an email inviting you to join this training then you should not try to book

This three and a half day course, will provide participants the necessary basic concepts to, describe the function of a digital design at the Register Transfer Level (RTL) using VHDL and perform FPGA prototyping using AMD Vivado.

This course is aimed at delegates that have no prior experience in digital design and no prior knowledge of Xilinx/Vivado. Theory and concepts are covered in lectures with significant time given to detailed hands-on practical exercises using the Xilinx Vivado FPGA tools. During the course participants will have the opportunity to design small digital components and verify them using a digital simulator (Vivado). During the second half of the course, delegates will explore a larger premade design and implement it onto an FPGA prototype board (Xilinx Zynq Z-7010 AP SoC).

The course schedule:

• Day 1 - 09:30 to 12:00 and 13:00 to 16:30 (UK local time)
  • VHDL Basics
  • Introduction to VHDL
  • Overview of VHDL, types, assignments and syntax
  • Hierarchical Design and Simulation
  • VHDL Process Statements

• Day 2 - 09:30 to 12:00 and 13:00 to 16:30 (UK local time)
  • VHDL basic testbench coding
  • Synthesisable VHDL code
  • Introduction to FPGA’s
  • FPGA technology

• Day 3 - 09:30 to 12:00 and 13:00 to 16:30 (UK local time)
  • Overview of the Vivado HDL flow
  • Timing Constraints
  • FPGA Clock creation
  • Using IP Blocks

• Day 4 - 09:30 to 12:00 (UK local time)
  • FPGA Design Management
  • In-System FPGA Hardware Debug

This course is aimed at delegates that have no prior experience in digital design and no prior knowledge of Xilinx/Vivado. However, an understanding of basic logic gates (AND, OR, NOR, etc.) and memory elements (flip flops and registers) is needed. Understanding of programming principles (loops, if statement etc.) is also required.