Front End and Verification Suite

The Front End and Verification suite from Synopsys consists of a collection of high performance synthesis, static timing and functional verification tools.

Product List

Front End and Verification Tools CentOS Linux
64bit
Redhat Enterprise Linux
64bit
SUSE Linux Enterprise
64bit
Windows
64bit
Design Compiler Elite Logical, topographical and graphical synthesis from RTL to netlist (includes Design Vision GUI, Design Compiler Ultra and Design Compiler NXT); includes Power Compiler for power optimisation and DFTMAX logic BIST add-on Yes Yes Yes -
TestMAX Integrated RTL to ATE implementation and verification flow. Includes TestMAX Access, TestMAX Advisor, TestMAX ATPG Elite, TestMAX DFT Apex, TestMAX Diagnosis, TestMAX FuSa Elite, TestMAX Manager, TestMAX SMS, TestMAX Vtran and TestMAX XLBIST Yes Yes Yes -
Formality Elite Formal equivalence checker; includes Formality ECO Elite and FuSa add-on Yes Yes Yes -
DesignWare Library of implementation and verification models Yes Yes Yes -
CoreAssembler & CoreBuilder Tools for IP block management and configuration Yes Yes Yes -
VCS Apex VHDL, Verilog, SystemVerilog and SystemC simulator; includes mixed language support and multi-core (FGP) technology. Yes, and 32 bit Yes, and 32 bit Yes, and 32 bit -
Synopsys Verification IP Verification IP coded in SystemVerilog, supporting VMM, UVM and OVM Yes, and 32 bit Yes, and 32 bit Yes, and 32 bit -
HAPS (software only) Tools for use with CHIPit and HAPS systems. Includes HAPS-60 Co-Sim & TBV Suite, HAPS-600/CHIPit Manager Ultra, HAPS-60 Transactor Runtime, HAPS-70 Co-Sim & TBV Suite, HAPS-70 Transactor Runtime, HAPS-DX TBV Suite, HAPS-DX Transactor Runtime, ProtoCompiler. Yes Yes Yes Yes
PrimeTime Apex Signoff quality gate-level static timing analysis and signal integrity analysis, supports multi-corner, multi-voltage analysis and aging-aware STA.
Yes Yes Yes -
PrimePower Elite Power analysis for block-level and full-chip designs from implementation to signoff
Yes Yes Yes -
PrimeClosure Apex Signoff ECO
Yes Yes Yes -
PrimeShield Spice2Design exploration/migration, robustness analysis and optimisation using fast Monte Carlo statistical simulation on critical paths Yes Yes Yes -
Verdi Apex Debug environment for both simulation and formal flows; includes fault analysis, performance analyzer, AMS, power-aware, portable stimulus, HAPS, and Zebu debug. Yes, and 32 bit Yes, and 32 bit Yes, and 32 bit -
Synplify Apex Synthesis of RTL (VHDL and Verilog) to FPGA targets and synthesis of ASIC designs for prototyping on FPGAs. Includes HDL Analyst for graphical representation and Identify RTL debugger for verification and cross-probing between RTL source and FPGA design. Yes Yes Yes Yes
DesignWare Library Library of key infrastructure IPs for SoC design and verification - Yes Yes Yes
PrimeSim XA
(formerly CustomSim)
Fastspice simulator for mixed-signal designs Yes Yes Yes -
NanoTime Transistor level static timing and SI analysis, characterization of custom digital, memories and AMS macros. Yes Yes Yes -
WaveView Elite Analogue / mixed-signal waveform viewer and transistor level debugging environment. Yes Yes Yes Yes
ESP Elite Transistor level formal equivalence checking of full-custom: memories, datapath and IO cells. Yes Yes Yes -
PrimeLib Library characterization suite (digital standard cells) Yes Yes Yes -
VC SpyGlass Apex RTL Lint analysis, advanced formal lint with clock domain crossing (CDC), netlist level CDC analysis and reset domain crossing (RDC) analysis Yes Yes Yes
Silver and TestWeaver Virtual ECU platform and system test automation for automotive systems. Yes Yes Yes Yes
Euclide Elite Design and verification integrated development environment (IDE) with on-the-fly RTL and UVM/SVTB lint checks. - Yes - Yes
Platform Architect Elite System modelling and development environment Yes Yes Yes Yes
Certitude Functional qualification of verification environment using fault injection to analyze and measure quality of VHDL, Verilog, SystemVerilog, SystemC and C/C++ test benches Yes, and 32 bit Yes, and 32 bit Yes, and 32 bit -
RTL Architect Elite Enables hierarchical RTL flow including fast synthesis, hierarchical floorplanning, RTL restructuring, constraints management, GUI debugging and parallel RTL exploration. Yes Yes Yes -
PowerReplay Early gate-level power analysis using RTL simulation data Platform independent
Timing Constraints Manager Apex SDC constraint generation, verification and management Yes Yes Yes -
VC Formal Elite Next generation formal property verification, SoC connectivity checks, sequential equivalence checking, register verification, X-propagation, coverage analysis, functional checks, testbench analysis and machine learning applications. Yes Yes Yes -
VC LP Elite UPF-based low power static rule checker Yes Yes Yes -
VC Portable Stimulus Allows users to describe test intent for different scenarios and to convert these to relevant stimulus Yes Yes Yes -
VC Functional Safety Manager Functional safety verification flow Yes Yes Yes Yes, and 32 bit
VC VIP SOC Library Base Library of bus, interface and memory verification IPs Yes Yes Yes -
Z01X Fault simulation for IEC 61508 and ISO 26262 compliance Yes Yes Yes -
Zebu Continuum Software for Zebu emulators Yes Yes Yes -

Important, please note that:


ASIP Designer

Product List

ASIP Designer (FEV suite add-on) CentOS Linux
64bit
Redhat Enterprise Linux
64bit
SUSE Linux Enterprise
64bit
Windows
64bit
ASIP Designer Application-specific instruction-set processors (ASIPs) development Yes Yes Yes Yes

Important, please note that:


Analogue Simulation & Modelling Suite

The Analogue Simulation & Modelling suite comprises tools for full custom design, circuit simulation and analysis.

Product List

Analogue Simulation and Modelling Tools CentOS Linux
64bit
Redhat Enterprise Linux
64bit
SUSE Linux Enterprise
64bit
Windows
64bit
Custom Compiler Apex Full custom schematic capture, simulation and layout environment (includles Custom Compiler SE and Custom Compiler ADV) Yes Yes Yes -
WaveView Elite Analogue / mixed-signal waveform viewer and transistor level debugging environment Yes Yes Yes Yes
PrimeSim HSPICE
(formerly HSPICE)
High accuracy analogue circuit Simulator Yes Yes Yes Yes
PrimeSim Pro Next generation FineSim Pro with advanced RC reduction, load models, and GPU acceleration Yes Yes Yes Yes
PrimeSim Reliability Analysis Reliability verification including static analogue and digital circuit checks (CCK), high sigma Monte Carlo analysis (AVA),static power/signal net resistance check (SPRES), dynamic EMIR analysis (EMIR), MOS againg analysis (MORSRA) Yes Yes Yes -
PrimeSim CCK Parametric checks, ERC, logic and timing diagnostics, SI and leakage checks Yes Yes Yes -
PrimeSim Custom Fault Transistor-level fault injection and analysis for test coverage improvement and/or to ensure functional safety for ICs per ISO 26262 guidelines Yes Yes Yes -
SaberES Designer Elite Desktop environment for Power Electronics DesignHarness Design and Verification tool built on SaberRD infrastructure and simulation capabilities. It uses a single database to enable Sub-System→System→Wiring→Bundle Design flow, with support for Harness Architectures and Wire Design Templates. - - - Yes
StarRC Apex Signoff extraction, with custom add-on
Yes Yes Yes -

Important, please note that:


ASIC Implementation Tool Suite

The Implementation Tool suite comprises tools for physical implementation of digital ICs.

Product List

ASIC Implementation Tools CentOS Linux
64bit
Redhat Enterprise Linux
64bit
SUSE Linux Enterprise
64bit
Windows
64bit
Fusion Compiler Elite An RTL-to-GDS solution for 5/4nm designs and above Yes Yes Yes -
IC Compiler II (ICC II) Elite Physical implementation for >4nm geometry processes, including placement, CTS, routing and optimisation engines. Machine learning and Fusion technologies are included. Yes Yes Yes -
StarRC Apex Signoff extraction for digital and 3DIC designs, 3nm and above Yes Yes Yes -
IC Validator Apex Signoff DRC or LVS checking with ML add-on Yes Yes Yes -
ICV Workbench High Speed hierarchical layout visualization and analysis tool. It allows viewing and editing GDSII and OASIS layouts from small IP blocks to full chip databases Yes Yes Yes Yes
QuickCap Elite Golden extraction reference for process exploration, device modelling, library characterisation and high-accuracy analogue blocks Yes Yes Yes -
3DIC Compiler 2.5D IC exploration, implementation and early analysis Yes Yes Yes -
LynxNXT Automation System Configuring tool flow automation Yes Yes Yes -
Design.da Apex Metrics capture and visualisation for digital implementation and signoff flows. Yes Yes Yes -
Timing Constraints Manager SDC constraint generation, verification and management Yes Yes Yes -

ASIC Implementation Tool Suite Notes:


Advanced TCAD Suite

Synopsys' Sentaurus Advanced TCAD suite provides an extensive suite of tools for semiconductor process and device modelling.

Product List

Advanced TCAD Tools CentOS Linux
64bit
Redhat Enterprise Linux
64bit
SUSE Linux Enterprise
64bit
Windows
64bit
Sentaurus Workbench Advanced Simulation environment for TCAD users; provides GUI to create, edit and execute TCAD projects; includes support for automatic generation of design of experiment splits, analysis and optimisation. Yes Yes - -
Sentaurus Visual Interactive 1D, 2D and 3D visualisation of TCAD structures and data Yes Yes - -
Sentaurus Process 2D and 3D silicon process simulator; supports major process steps such as implantation, oxidation, diffusion and geometrical etching and deposition Yes Yes - -
Sentaurus Process Kinetic MC Process simulator using an atomistic approach to dopant, point defect and extended defect interactions Yes Yes - -
Sentaurus Device Multidimensional device simulator. Includes Advanced, 3D, DSM, Compound, Parallel, EMW, Power, Monte Carlo, QTX and Spintronics options Yes Yes - -
Sentaurus Structure Editor Multidimensional process emulator and graphical device structure editor. Includes 3D option Yes Yes - -
Sentaurus PCM Studio and PCM Library Builds process compact models for parametric yield analysis - Yes - Yes
Raphael-FX RC extraction in interconnect structures Yes Yes - -
Sentaurus Topography Simulator for physical modelling of topography-modifying process steps such as deposition and etching Yes Yes - -
Garand 3D device simulator for variability analysis; 3D ensemble Monte Carlo device simulator Yes Yes - -
S-Litho Lithography process simulation for proximity printing, DUV and e-beam direct write pattern applications; includes support for topographic masks (M3D) and structured substrates Yes Yes Yes Yes
S-Metro Enables direct import of CD-SEM metrology data for visualisation and analysis Yes Yes Yes Yes

Please note:


QuantumATK

Synopsys' QuantumATK is a complete and fully integrated software toolkit for atomic-scale modelling.

Details of the QuantumATK tool bundle can be found in the QuantumATK Datasheet

Product List

QuantumATK CentOS Linux
64bit
Redhat Enterprise Linux
64bit
SUSE Linux Enterprise
64bit
Windows
64bit
QuantumATK Simulation environment for density functional theory using pseudo-potentials, linear combinations of atomic orbitals (LCAO) basis sets and semi-empirical potentials; includes NEGF transport. Yes Yes Yes Yes

Synopsys Photonic IC (PIC) Platform

The Photonic IC (PIC) Platform is a comprehensive suite of solutions for design and simulation of Photonic ICs (PICs).

Product List

Photonic IC CentOS Linux
64bit
Redhat Enterprise Linux
64bit
SUSE Linux Enterprise
64bit
Windows
64bit
OptoCompiler Photonic IC design platform containing OptoCompiler, OptSim and Photonic Device Compiler. Yes Yes - -
IC Validator Elite Signoff DRC or LVS checking. Yes Yes - -

Please note:


Synopsys Simpleware

The Simpleware ScanIP Platform provides an extensive selection of image visualisation, measurement and processing tools for working with 3D and 4D image data.

Details of the Simpleware bundle can be found in the following datasheet.

The following recorded webinar provides an overview of the latest release of the Simpleware University Bundle:

Product List

Simpleware CentOS Linux
64bit
Redhat Enterprise Linux
64bit
SUSE Linux Enterprise
64bit
Windows
64bit
ScanIP Core image processing platform yes yes - yes
AS Cardio Provides anatomy-specific automated segmentation tools for CT data of the cardiovascular system data yes yes - yes
AS Ortho Provides anatomy-specific automated segmentation tools for CT data of the orthopedic and craniomaxillofacial data yes yes - yes
Simpleware FE Mesh generation from segmented image data yes yes - yes
Design Link Enables speed-up in workflows between SOLIDWORKS® and ScanIP - - - yes
CAD* Enables CAD integration yes yes - yes
NURBS* Supports NURBS model export yes yes - yes

* Available from the 2024.06 release.