IC Package
The IC package includes a wide range of tools for digital, analogue and mixed signal design and implementation.
For analogue and mixed-signal designers, this package includes tools for: Spice/fast-spice/mixed-signal simulation (Spice, Verilog-A/AMS, VHDLAMS), Spice RF analysis, schematic capture, simulation management (including montecarlo analysis), custom characterisation environment, circuit optimisation, yield optimisation, parametric sensitivity analysis, layout editing, schematic driven layout (constraint aware), complex device module generators (MODGENs), full custom floorplanning, cell/block placer, layout migration, cell/chip routing, interactive DRC, extraction (RCLK), LVS, DRC, electromigration analysis and IR Drop analysis.
For digital designers this package includes tools for: logic simulation (covering VHDL, Verilog, SystemC, SystemVerilog, SVA, PSL and e), formal property
proof, verification planning and management (and Verification IP), SDC checking and exception generation, CDC checking, RTL (Verilog, SystemVerilog and VHDL)
synthesis, high level (C/C++/SystemC) synthesis, test insertion, physical implementation (Placement, CTS, Routing, and Optimisation), logical equivalence checking, RC
extraction, DRC, LVS, signoff timing analysis, signoff power analysis, standard cell library characterisation/re-characterisation, and ATPG.
Product List
| IC Package 2025 | Release Name | Key Tools | Supported Platforms * |
|---|---|---|---|
| Linux (lnx86) | |||
| Analog/Full Custom Design Tools | Virtuoso Studio® Custom Design Platform IC 23.1 |
- Virtuoso Schematic family of products enabling design and constraint composition - ADE Explorer, Assembler and Verifier for simulation setup and specification driven design - ViVA waveform viewer and analysis - Virtuoso Layout editor suite which allows for Connectivity-Driven & Constraint-Driven layout Entry including Electrically aware layout and editing - Voltus-XFi custom Power Integrity Solution, a transistor-level EM-IR tool |
RHEL 7, 8, 9 |
| Spectre® SPECTRE 24.1 |
- Spectre Accelerated Parallel Simulator (APS) - Spectre X simulator - Spectre Extensive partitioning Simulator (XPS) - Spectre AMS Designer - Spectre RF option - Spectre CPU Accelerator option - Spectre Power option |
RHEL 8, 9 | |
| EMX® Planar 3D Solver EMX 2024.1 |
- Electromagnetic simulator for high-frequency, RF and mixed-signal integrated Circuits | RHEL 7.4, 8 | |
| Verification IP | Verification IP Catalog VIPCAT 11.3 |
- Verification IP for a range of protocols for server, networking and storage interfaces | RHEL 7, 8 |
| Logic Design & Functional Verification | Xcelium Parallel Logic Simulation XCELIUM 24.03 |
- Parallel Logic simulation | RHEL 7.4, 8.1, 8.3, 8.4, 8.6. 8.8, 9 |
| Verisium Debug Platform VERISIUMDEBUG 24.03 |
- Addresses RTL, testbench, VIP and S0C verification debug | RHEL 7, 8 | |
| vManager Metric-Driven Signoff Platform VMANAGER 24.03 |
- Verification planning and Management | RHEL 7, 8 | |
| Digital Design & Synthesis Tools | Conformal Constraint Designer & Formal Equivalence Checker CONFRML 24.1 |
- SDC Timing constraints and clock specification - Formal Equivalence Checking - Low Power Verification - ECO Verification |
RHEL 7, 8, 9 |
| Conformal® Litmus LITMUS 23.2 |
- CDC signoff - Constraints signoff - Signoff static timer integration - Multi-CPU parallelisation |
RHEL 7, 8, 9 | |
| Genus™ Synthesis Solution DDIEXPORT 23.31 |
- Massively Parallel RTL synthesis and physical synthesis | RHEL 7, 8, 9 | |
| Joules™ RTL Power Solution DDIEXPORT 23.31 |
- Unified power calculator for accurate RTL power and signoff-quality gate power | RHEL 7, 8, 9 | |
| Digital Implementation Tools | Modus Test Solution MODUS 23.1 |
- Design for test - Automated Test Pattern Generation |
RHEL 7, 8, 9 |
| Silicon Signoff & Verification SSV 23.1 |
- Tempus Static Timing Analysis - Voltus Power Integrity analysis |
RHEL 7, 8, 9 | |
| Virtuoso Library Characterisation LIBERATE 23.1 |
- Library characterisation & validation | RHEL 7, 8, 9 | |
| Innovus™ Implementation System DDIEXPORT 23.31 |
- Place & Route / Digital Physical Implementation | RHEL 7, 8, 9 | |
| Physical Verification | Assura® Physical Verification ASSURA 4.17 |
- DRC & LVS for node sizes greater than 90nm | RHEL 7, 8, 9 |
| Physical Verification System PVS 24.1 |
- DRC & LVS for node sizes less than 90nm | RHEL 7.4, 8, 9 | |
| Pegasus Verification System PEGASUS 24.1 |
- DRC & LVS - Massively parallel architecture - In-design and signoff DRC from the Virtuoso and Innovus platforms |
RHEL 7.4, 8, 9 | |
| Quantus™ Extraction QUANTUS 23.1 |
- Parasitic Extraction & Analysis | RHEL 7, 8, 9 | |
| Pegasus DFM PEGASUSDFM 24.1 |
- Design for manufacture | RHEL 7, 8, 9 |
Systems Package
The systems package includes a wide range of tools for PCB design.
This package includes tools for: design entry (schematics, HDLs or spreadsheet), constraint entry and management, digital simulation (VHDL, Verilog), board layout, track
routing, analogue/mixed-signal simulation, power integrity analysis, signal integrity analysis, symbol library development and management, and a standard footprint parts library
Product List
| Systems Package 2025 | Release Name | Key Tools | Supported Platforms * | |
|---|---|---|---|---|
| Linux (lnx86) | Windows (Server 2019, Server 2022, 10, 11) |
|||
| PCB Design | System, Package & Board SPB 24.1 |
- Allegro X | RHEL 8.4, 9 | Yes |
| Signal & Power Integrity | Allegro® Sigrity™ SIGRITY 2024.1 |
- Power-aware Signal Integrity analysis with PowerSI - PowerSI 3D EM Full-Wave Extraction - PowerSI 3D EM Full-Wave Extraction - IC package model extraction with XtractIM - Optimality Explorer Essentials - Celsisus Thermal Solver |
RHEL 8.4, 9 | Yes |
| Verification IP | Verification IP Catalog VIPCAT 11.3 |
- This release includes verification IP for a range of protocols for server, networking and storage interfaces | RHEL 7, 8 | No |
| Logic Design & Functional Verification | Xcelium Parallel Logic Simulation XCELIUM 24.03 |
- Parallel Logic simulation | RHEL 7.4, 8.1, 8.3, 8.4, 8.6, 8.8, 9 | No |
| vManager Metric-Driven Signoff Platform VMANAGER 24.03 |
- Verification planning and Management | RHEL 7, 8 | No | |
PCB Studio Package
The PCB studio package provides an alternative PCB design environment, supporting the Microsoft Windows environment.
The package includes tools for: design entry, board layout, routing up to 6 metal layers, spice simulation, and entry level interconnect analysis.
Product List
| PCB Package 2025 | Release Name | Key Tools | Supported Platforms * |
|---|---|---|---|
| Windows (Server 2019, Server 2022, 10, 11) |
|||
| PCB Design | System, Package & Board SPB 24.1 |
- Allegro X | Yes |
| Signal & Power Integrity | Allegro® Sigrity™ SIGRITY 2024.1 |
- Signal Integrity Analysis | Yes |
* For further information on the End of Life schedule for releases marked as 'legacy', please contact MicroelectronicsCentre@stfc.ac.uk