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On-Demand Training Available

The Microelectronics Support Centre at STFC Rutherford Appleton Laboratory is pleased to announce a pilot to make available access to Siemens EDA On-Demand Training Libraries for a subset of the tools provided through Europractice.

These libraries are educational resources based upon Siemens EDA tools. They contain video lectures, lab exercises, and knowledge checking tests, at multiple stages of various tool chain flows.
The available labs are simple to set up and use as they're hosted in the cloud, connecting the user through to virtual machines with all of the required tools installed already.

This scheme is initially only being rolled out for Europractice members with existing Europractice/Siemens EDA End-User License agreements on a first come first served basis. Siemens EDA will be able to monitor usage and at the end of the pilot STFC Europractice will ask for feedback to help persuade Siemens EDA to expand the offering and make it available to the entire Europractice membership.

Currently the training libraries that will be made available are associated with Calibre, Catapult, Eldo, Functional Verification, HyperLynx tools, Xpedition and Tanner EDA (L-Edit).

Europractice Representatives can nominate colleagues for access to the pilot scheme via our Member Only Web Pages (login required)

Siemens EDA Full Suite

Full List

The Siemens EDA Full suite package comprises of a comprehensive suite of tools that cover a wide range of design flows and areas including the following and more:

Product Description Supported Platform
Digital IC Design
Oasys-RTL Oasys-RTL provides better quality of results by enabling physical accuracy, floorplanning, and fast optimization iterations to get to design closure on time. RHEL 6.x/7.x
CentOS 6.x/7.x
Nitro-SoC The Nitro-SoC netlist-to-GDSII system comprehensively addresses the performance, capacity, time-to-market, power, and variability challenges encountered at the leading-edge process nodes. It has a high-capacity architecture, a native sign-off quality timer with patented virtual timing graph technology, and best-in-class physical implementation engines. Windows 8/8.1/10
CentOS 4.x/5.x/6.x
Custom IC Design
Tanner S-Edit Tanner S-Edit is an easy-to-use design environment for schematic capture and design entry. It gives you the power you need to handle your most complex mixed-signal IC design capture. Windows 8/8.1/10
RHEL 6.x/7.x
Tanner L-Edit Tanner L-Edit IC is an analogue/mixed-signal (AMS) IC physical design environment that gives you all the features you need to quickly and efficiently finish the layout of your design. Windows 8/8.1/10
RHEL 6.x/7.x
Tanner T-Spice Tanner T-Spice Circuit Simulator puts you in control of simulation jobs, with an easy-to-use graphical interface and a faster, more intuitive design environment. Windows 8/8.1/10
RHEL 6.x/7.x
PCB Design and Verification
Xpedition Enterprise Xpedition Enterprise is an innovative PCB design flow, providing integration from system design definition to manufacturing execution. Its unique technologies can reduce design cycles by 50 percent or more while significantly improving overall quality and resource efficiency. Windows 8/8.1/10
RHEL 6.x/7.x
HyperLynx HyperLynx is industry-renowned for ease of use, with automated workflows that make sophisticated PCB analysis accessible to designers who are new to power and signal integrity analysis. Windows 8/8.1/10
RHEL 6.x/7.x
FPGA Design and Synthesis
Precision Precision Synthesis solutions from Siemens provides high-quality Verilog/VHDL/SystemVerilog synthesis for the latest FPGAs, easy-to-use debug and validation environment, comprehensive & user-friendly high-reliability synthesis, and tight integration with Siemens Catapult HLS & FormalPro LEC tools. Windows 8.1/10
RHEL 6.x/7.x/8.1
SLES 12.0
CentOS 6.x/7.x
Leonardo LeonardoSpectrum is a suite of high-level design tools for a CPLD, FPGA, or ASIC. The tool offers design capture, VHDL and Verilog entry, register- transfer-level debugging for logic synthesis, constraint-based optimization, timing analysis, encapsulated place-and-route, and schematic viewing. Windows 7/10
RHEL 5.x/6.x/7.x
Analogue/Mixed Signal Verification
Eldo Industry-proven platform for analogue-centric circuits, offering a differentiated solution for reliability verification and comprehensive circuit analysis and diagnostics for analogue, RF, and mixed-signal circuits. RHEL 6.5+/7.x/8.x
SLES 11.4/12
Questa ADMS Works exclusively with Eldo to extend Questa Verification Platform to analogue and mixed-signal, providing a comprehensive environment for verifying complex AMS SoCs. RHEL 6.5+/7.x/8.x
SLES 11.4/12
Calibre nmDRC The Calibre Physical Verification platform provides you with a comprehensive, innovative verification technology for all nodes and processes. RHEL 5.x/6.x/7.x/8.x
CentOS 5.x/6.x/7.x/9.x/10.x
Calibre nmLVS The Calibre circuit verification toolsuite includes layout vs. schematic checking, reliability verification, and parasitic extraction. RHEL 5.x/6.x/7.x/8.x
CentOS 5.x/6.x/7.x/9.x/10.x
Calibre xACT Calibre xACT is a high-performance, high-accuracy parasitic extraction tool for leading-edge transistor-level and digital design. RHEL 5.x/6.x/7.x/8.x
CentOS 5.x/6.x/7.x/9.x/10.x
Functional Verification
Questa Simulation Questa simulation spans all levels of design and verification abstraction and supports multiple verification methodologies and languages to increase testbench productivity, automation, and reusability. Windows 10
RHEL 7.x/8.x
Questa Formal Questa Formal Verification Apps boost verification efficiency and design quality by exhaustively addressing verification tasks which are difficult to complete with traditional methods, yet do not require formal or assertion-based verification experience. Windows 10
RHEL 7.x/8.x
High-Level Synthesis
Catapult Ultra Industry leading C++/SystemC High-Level Synthesis with Low-Power estimation/optimization. Design checking, code and functional coverage verification plus formal make HLS more than mere “C to RTL. RHEL 5.x/6.x
Vista Vista is a native Electronic System Level (ESL) platform for architecture design, verification, analysis, and virtual prototyping that incorporates an advanced design, verification, and analysis toolset targeted for high-level transaction-level modelling (TLM) hardware platforms. Windows 10
RHEL 7.x
Silicon Test
Tessent Design augmentation and linked applications that detect, mitigate, and eliminate risks throughout the IC lifecycle, helping customers address their debug, test, yield, safety, security, and optimization requirements for today’s most complex SoCs. RHEL 6-6.6
CentOS 6-6.6

FPGA and Board

Full List

The FPGA and Board package consists of a subsection of the Full Suite tools that focus primarily on FPGA and PCB work.

Siemens EDA Online Support and Resources

Siemens EDA provides an extensive collection of documents and resources that are made readily available to their tool users at their Siemens EDA Support Centre website, these include tool user guides, command references, and frequently asked questions with solutions. The Siemens EDA Training page gives access to hundreds of hours of on-demand training content featuring video lectures, online virtual labs, and knowledge tests with feedback.

- Siemens EDA Online Support
- Siemens EDA Online Training

Sign up to join the Siemens EDA On-Demand Training Pilot, giving you access to Calibre, Tanner EDA (L-Edit), Xpedition, and HyperLynx training material.