Imperas provide Virtual Prototyping technology for generating Virtual Platforms that can be used for embedded software development. Imperas make available fast processor models through the OVP (Open Virtual Platforms) initiative www.OVPWorld.org.
The Imperas/OVP processor models cannot be used directly, but require a simulator. There are two Imperas simulators available; the "lite" simulator (OVPsim), and the fully featured simulator (M*DEV). We also provide QuantumLeap, which is also an option to M*DEV which further speeds up simulation of multi-core systems.
The three Imperas products that are available through Europractice are:
OVPsim is the "lite" simulator that provides multi-core simulation, and single core debug support for OVP platforms. Please note, a FREE 60 day node-locked license license for OVPsim can be obtained via the OVPworld website. Annually renewable node-lock and floating licenses for OVPsim are available through Europractice.
M*DEV is the professional version of the Imperas simulator and implements the complete OVP API, providing additional optimisations and capabilities compared to OVPsim. It supports single-core and multi-core systems (both homogeneous and heterogeneous) with full debug support.
QuantumLeap is an add-on for M*DEV to speed up simulation of multicore OVP system models by efficiently distributing simulated cores across the physical cores in a host machine. The accelerator includes both ToolMorphing and SlipStreamer™ capabilities, such that the full tool suite operates with minimal impact to performance and no adverse effect on simulated software operation.
Imperas/OVP Processor Models and Virtual Platforms
Virtual Platforms are models of a system that can be created before RTL is available and are used for system partitioning, optimisation, and software development. Virtual Platforms rely on fast processor models to allow simulation speeds of 100's-1000's MIPS, allowing interactive debug and verification of embedded software. Imperas provide processor models for over 130 processors, including ARM, Imagination MIPS, Renesas, PowerPC, openCores, Altera Nios II, Xilinx Microblaze and Synopsys ARC.
Imperas/OVP Processor Models
All Imperas/OVP Fast Processor Models support the GDB interface, and include a native SystemC/TLM-2.0 interface, enabling easy use in SystemC simulation environments. As well as processor models, platform, memory and peripheral libraries are also included.
The Peripheral Library has over 40 components that can be used to build a custom platform. Peripherals range from simple timers, to full functionality of an Ethernet controller that connects to the host ethernet port and provides network/internet access from within the simulation.
The platform library includes example platforms that can be used to boot complete operating systems.
Supported processors include:
Altera Nios II/f, Nios II/s, Nios II/e - verified with Altera test suite