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Front End and Verification Suite

The Front End and Verification suite from Synopsys consists of a collection of high performance synthesis, static timing and functional verification tools.

Product list

Front End and Verification Tools Redhat Enterprise Linux SUSE Linux Enterprise  Windows  
Design Compiler Graphical Logical, topographical and graphical synthesis from RTL to netlist (includes Design Vision GUI, Design Compiler Ultra and Design Compiler Graphical). 64 bit 64 bit -
Power Compiler Power optimization option to Design Compiler. 64 bit 64 bit -
DFTMax, Ultra & LogicBIST Test option to Design Compiler. Includes scan test insertion; Boundary scan test insertion; including very high compressed scan test synthesis and built-in self test for logic 64 bit 64 bit -

TetraMax

Automatic test pattern generation providing support for traditional ATPG, IDDQ and at-speed tests; supports DFTMax Ultra scan compression.

64 bit 64 bit -
Formality Formal equivalence checker 64 bit 64 bit -
DesignWare Library of implementation and verification models 64 bit 64 bit -
CoreAssembler & CoreBuilder Tools for IP block management and configuration 32 & 64 bit 64 bit -
VCS-MX VHDL, Verilog, System Verilog and System C simulator 32 & 64 bit 32 & 64 bit -
VCS NLP Voltage-aware simulation for VCS for designs which implement UPF power management techniques 32 & 64 bit - -
Synopsys Verification IP Verification IP coded in SystemVerilog, supporting VMM, UVM and OVM 32 & 64 bit - -
VC-LP Verification Compiler Low Power. Static checking of power intent for designs that use UPF power intent. 32 & 64 bit 32 & 64 bit -
HAPS (software only) Tools for use with CHIPit and HAPS systems. Includes HAPS-60 Co-Sim & TBV Suite, HAPS-600/CHIPit Manager Ultra, HAPS-60 Transactor Runtime, HAPS-70 Co-Sim & TBV Suite, HAPS-70 Transactor Runtime, HAPS-DX TBV Suite, HAPS-DX Transactor Runtime, ProtoCompiler. 32 & 64 bit 32 & 64 bit 32 & 64 bit
PrimeTime ADV,
PrimeTime PX,
PrimeTime Constraint Consistency
Gate-level static timing analysis and signoff with SI analysis;
Full chip gate level power analysis;
SDC timing constraint consistency checking
64 bit 64 bit -

Verdi, Verdi Power Aware Debug & Verdi HW SW Debug

Debug automation for digital designs including debug (visualization, tracing and analysis) of UPF/CPF power intent

32 & 64 bit 32 & 64 bit -

Siloti, Siloti Replay & Siloti Correlation

Visibility enhancement automation; Improves simulation speed by automatically identifying a reduced set of signals to trace during simulation. Includes on-demand generation of the full waveform data from the minimal waveform datasets. Cross-correlation of netlist simulation with trace back to the RTL.

32 & 64 bit 32 & 64 bit -

Milkyway

Design and technology database

64 bit 64 bit -
Synplify Premier DP AV Synthesis of RTL (VHDL and Verilog) to FPGA targets 32 & 64 bit 32 & 64 bit 32 & 64 bit
Synphony Model Compiler ASIC DSP Algorithmic synthesis 32 & 64 bit 32 & 64 bit 32 & 64 bit
DesignWare TLM Library; DesignWare ARM TLM Library Library of transaction level models;
Library of ARM / AMBA transaction level models
32 & 64 bit - 32 bit

CustomSim

Fastspice simulator

64 bit 64 bit -
NanoTime Transistor level static timing analysis 32 & 64 bit 32 & 64 bit -

Custom WaveView ADV

Analogue / mixed-signal waveform viewer and transistor level debugging environment.

64 bit 64 bit 64 bit
ESPCV Transistor level formal equivalence checking of full-custom: memories, datapath and IO cells. 64 bit 64 bit -

Silicon Smart ADV

Library characterization suite (digital standard cells)

32 & 64 bit - -

SpyGlass

A collection of tools aimed at enabling early design closure at the RTL level.

32 & 64 bit - -

Important, please note that:

  1. System Studio and associated libraries are included within 2017 key files but will be deleted at 31 December 2017.
  2. SpyGlass included within FEV from 1st January 2018.


Analogue Simulation & Modelling Suite

The Analogue Simulation & Modelling suite comprises tools for full custom design, circuit simulation and analysis.

Product list

Analogue Simulation and Modelling Tools Redhat Enterprise Linux SUSE Linux Enterprise   Windows  
Custom Compiler (including Custom Compiler SE and Custom Compiler ADV) Full custom schematic capture, simulation and layout environment 64 bit 64 bit -

Custom WaveView ADV

Analogue / mixed-signal waveform viewer and transistor level debugging environment.

64 bit 64 bit 64 bit
HSPICE Circuit Simulator and GUI 32 & 64 bit 32 & 64 bit 32 & 64 bit
FineSim SPICE simulator FineSim 64 bit 64 bit -

CustomSim

Fastspice simulator

64 bit 64 bit -
CustomSim CircuitCheck (CCK) Spice static circuit checks (Using XA for static checks and HSIM for dynamic checks). Note: FineSim also provides a range of circuit checks 64 bit 64 bit -
Saber Mixed-Signal Simulator including Saber ES, Saber MAST HDL and VHDL-AMS co-simulation. Interactive graphical user interface and schematic entry for Saber. Saber DX and SL Component Libraries and Optional Template Libraries. Transient, Monte Carlo, Sensitivity, Stress Fourier FFT and distortion Analysis 32 bit 32 bit 32 bit & 64 bit
SaberRD Desktop environment for Power Electronics Design - - 32 bit & 64 bit

Important, please note that:

  1. Custom Compiler replaces Custom Designer.
  2. Users of Laker Tools (Laker3 ADP, Layout, Analogue Prototyping, Custom Row placer and Router, Blitz and FPD) are encouraged to migrate to CustomCompiler.
  3. RC extration capability requires StarRC from the ASIC Implementation Suite.
  4. Sign-off DRC and LVS requires ICvalidator or Hercules from the ASIC Implementation Suite.


ASIC Implementation Tool Suite

The Implementation Tool suite comprises tools for physical implementation of digital ICs.

Product list

ASIC Implementation Tools Redhat Enterprise Linux SUSE Linux Enterprise  Windows  
IC Compiler including advanced geometry option (see note 1) Physical implementation for small geometry processes 64 bit 64 bit 64 bit
PrimeRail Full chip static and dynamic power network analysis and signoff 64 bit 64 bit -
StarRC Ultra Full chip RC extraction 64 bit 64 bit -
IC Validator ADV Hierarchal physical verification 64 bit 64 bit -
Hercules Hierarchal physical verification 32 & 64 bit 32 & 64 bit -
Galaxy Custom Router Enables custom routing of digital designs using the CustomDesigner environment 32 & 64 bit 32 & 64 bit -
IC WorkBench ev Plus High Speed hierarchical layout visualization and analysis tool. It allows viewing and editing GDSII and OASIS layouts from small IP blocks to full chip databases 64 bit 64 bit 64 bit
Milkyway Design and technology database 64 bit 64 bit -

ASIC Implementation Tool Suite Notes:

  1. Synopsys offer fully featured flows for physical implementation of digital ICs down to the smallest geometries. For 20nm and larger geometries this is based on IC Compiler including the advanced geometry option. However, universities working on advanced technology node designs (14nm and below) can submit requests for additional Synopsys tools. Requests should be made on official university letterhead and include brief description of the project including collaborators (if any), details of the wider design flow, the exact IC process targeted and project timeline. Requests should be sent to MicroelectronicsCentre@stfc.ac.uk who will pass the details to Synopsys for consideration.


Advanced TCAD Suite

Synopsys' Sentaurus Advanced TCAD suite provides an extensive suite of tools for semiconductor process and device modelling.

Product list

Advanced TCAD Tools Redhat Enterprise Linux SUSE Linux Enterprise  Windows  
Sentaurus Workbench Advanced Framework tool for the co-ordination and analysis of multiple simulation runs 64 bit 64 bit -
Sentaurus Visual Visualisation tools 64 bit 64 bit -
Sentaurus Process Multidimensional semiconductor process simulator. Includes 3D option 64 bit 64 bit -
Sentaurus Process Kinetic MC Atomistic kinetic Monte Carlo implantation and diffusion simulator 64 bit 64 bit -
Sentaurus Device Multidimensional device simulator. Includes Advanced, 3D, DSM, Compound, Parallel, EMW, Power and Monte Carlo options 64 bit 64 bit -
Sentaurus Structure Editor Multidimensional process emulator and graphical device structure editor. Includes 3D option 64 bit 64 bit -
Sentaurus PCM Studio and PCM Library Builds process compact models for parametric yield analysis 32 & 64 bit - 32 bit
IC WorkBench ev Plus High Speed hierarchical layout visualization and analysis tool. It allows viewing and editing GDSII and OASIS layouts from small IP blocks to full chip databases 64 bit 64 bit 64 bit
Taurus Medici (2D) 2D Device simulation tool 64 bit - -
Taurus TSUPREM-4 (2D) 2D Process simulation tool 64 bit - -
Raphael 2D/3D field solvers for interconnect 64 bit - -


Synopsys Synplify FPGA Tools

The FPGA tools suite comprises tools for FPGA implementation and DSP design.
Please note: The tools within this Synopsys Synplify FPGA Tools are also included within the FEV Suite.

Product list

Synopsys Synplify FPGA Tools Redhat Enterprise Linux SUSE Linux Enterprise  Windows  
Synplify Premier DP AV Synthesis of RTL (VHDL and Verilog) to FPGA targets and synthesis of ASIC designs for prototyping on FPGAs. Includes HDL Analyst for graphical representation and Identify RTL debugger for verification and cross-probing between RTL source and FPGA design 32 & 64 bit 32 & 64 bit 32 & 64 bit
Synphony Model Compiler ASIC DSP Algorithmic synthesis 32 & 64 bit 32 & 64 bit 32 & 64 bit


System Level Suite

Platform Architect is a SystemC modelling and development environment for hardware/software co-design. Linked with Virtualizer, this allows the building and management of virtual prototypes.

Product list

System Level Suite Tools Redhat Enterprise Linux SUSE Linux Enterprise  Windows  
Platform Architect System modelling and development environment 32 & 64 bit 32 & 64 bit 32 & 64 bit
TLM Libraries ARM TLM Library (ARM7, ARM9 and ARM11 processors), Renesas TLM Library (SH4a,V850 processors), Infineon TLM library (Tricore 1.3.1 processor). TLM processor models are configurable and instrumented for analysis and debug visibility. 32 & 64 bit 32 & 64 bit 32 & 64 bit
DesignWare TLM library DesignWare TLM library 32 & 64 bit 32 & 64 bit 32 & 64 bit
AMBA TLM Library AMBA 2.0 TLM base library, AMBA 3 AXI TLM base library and AMBA 4 base library 32 & 64 bit 32 & 64 bit 32 & 64 bit
Virtualizer Virtualizer and Virtualizer Dev Kit Plus (VDK+) 32 & 64 bit 32 & 64 bit 32 & 64 bit

Important, please note that:

  1. Processor Designer is included within 2017 year key files but will be deleted at 31 December 2017.
  2. SPW and associated libraries are included within 2017 year key files but will be deleted at 31 December 2017.





STFC Home page Europractice membership and design tools access is managed by STFC at the Microelectronics Support Centre, Rutherford Appleton Laboratory, UK. You can contact the Microelectronics Support Centre by email: MicroelectronicsCentre@stfc.ac.uk

Last modified: September 18, 2017