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FPGA and Board Design (FPGA)
FPGA and Board Design flow comprises of the following environment flows;
Digital Design & Verification
HDL Designer is a design environment for Verilog/VHDL code development, analysis and management, with automation for running Questa for simulation and Precision for FPGA synthesis. It includes the following features; design management, source code entry, graphical code development (FSM design, Spreadsheet IO entry, Schematic assembly) and HDL Linting (DesignChecker). These tools assist with IP reuse and multi-site design by ensuring a standard design environment.
- Questa (formerly known as ModelSim) is an advanced verification environment. The Questa verification libraries simplify Assertion-based verification (ABV) and promotes higher quality and faster time-to-debug. Integrated debug and analysis using SystemVerilog, SystemC, VHDL, Verilog, PSL, UPF and C/C++. A comparison with the Europractice supported tool, ModelSim SE can be seen here.
- Questa Core/Prime Is a digital simulator which supports Verilog, SystemVerilog, VHDL and SystemC. It includes a graphical debug environment which supports advanced verification techniques such as TLM, assertion-based verification, UVM and OVM.
- Leonardo Spectrum is a synthesis tool for FPGA and ASIC implementation, however this product is being phased out and users should use Precision Synthesis where possible. Key features include; VHDL and Verilog support.
- Precision Synthesis
provides advanced FPGA synthesis capabilities, with physically aware synthesis capabilities (Precision RTL Plus). Key features include VHDL, Verilog and SystemVerilog support, incremental synthesis and Low Power Synthesis. Precision also includes the Precise-IP, a library of FPGA independent configurable IP for use with Precision Synthesis.
PCB Design tools & Verification
- Xpedition TM Enterprise combines the integrated flow from the system design definition to the manufacturing execution. Design challenges including differential pair routing, controlled impedance, net scheduling, delay net tuning, manufacturing optimization, flex circuits, embedded passives and microvias (including vias in pads and via spans between any two layers) are all possible using constraint driven rules and technology files. These constraints are shared between schematic capture and layout tools and provide a consistent approach at any time in the design stage.
- Incorporating xDX Designer which provides schematic capture capability for complex hierarchical designs. With a unified front end design environment xDX Designer integrates component and design data, reducing part selection errors and reduces design development times.
- The Constraint Manager (formally CES) provides a comprehensive and intuitive environment in which to analysis crosstalk, create differential pairs and other signal integrity requirements. Fully integrated into the xDXDesigner and Xpedition environments, this spreadsheet based constraint interface allows bi-directional cross probing and offers an extremely efficient method of capturing the design intent.
- xDX I/O Designer integrated within Expedition, xDX I/O Designer optimses the design process from FPGA design to PCB design. The generation of fast and easy PCB symbols with correct-by-construction I/O assignment using up-to-date vendor devices greatly reduces the time taken with today’s high pin counts FPGA's.
- Xpedition PCB maintains data integrity from concept to manufacturing by delivering a new standard in scaleable tools for the layout, analysis, and manufacture of highly complex PCBs.
- HyperLynx DRC with 19 standard design rule checks for items such as traces crossing splits, reference plane changes, shielding and via checks, HyperLynxDRC is highly customizable on boards that could potentially contain EMI/EMC issues.
- HyperLynx SI Addressing high speed PCB signal integrity issues at the earliest architectural stages and right through to post-layout verification, ensures designs are right first time.
- HyperLynx PI With an increasing number of power voltages used on modern electronic designs, with the potential dramatic increase in power consumption, designers using HyperLynx PI can identify power distribution problems early in the design, minizing prototype spins and creating more reliable products.
- HyperLynx Thermal allows the designer to evaluate board level thermal problems from pre or post routed boards. Examining a board's temperature profile, gradients and excess temperature maps, allows the designer to avoid overheating problems early in the board design process.
Advanced Digital Functional Verification
- Questa CDC is a clock domain crossing (CDC) analysis tool, and is designed to detect CDC bugs that are not detectable using simulation alone. It does this by identifying clocks and clock domain crossings in the design and performs structural analysis to check synchronization schemes and identify any missing synchronizers. It then uses formal analysis to perform protocol verification (for the specific type of synchronization scheme) and re-convergence verification to check that re-convergent signals are not synchronized separately. Finally it adds the capability to simulate the effects of CDC-Jitter on the functional logic of your design by injecting CDC jitter into your traditional simulations.
- Questa InFact Is an intelligent test bench automation tool that can be integrated into existing test benches to target functional coverage holes to achieve coverage closure.
- Reqtracer is a design requirement management tool used in both FPGA and ASIC design flows. It aims to provide traceability between functional specification, hardware implementation and test bench codes.
- Visualizer Debug Environment Visualizer Debug Environment is a high performance digital debug environment with advanced capabilities to ease the debugging of large SoC and FPGA based designs. It provides high capacity, high performance waveform viewing, with a range of advanced features, including; causality tracing (to back-trace error values), transaction level debugging (UVM aware), with transaction stripe views for testbench debugging, and improved debug productivity for RTL, gate level and low power design and verification.
Full Suite (Full)
The Full Suite flow comprises a number of different environment flows and includes the FPGA & Board Design tools, described in the above section;
HYperLynx 3D EM Field Solver
- HyperLynx 3D EM SSD is an industry-standard EM design and analysis package, based upon a full-wave 3D method-of-moments solver. HyperLynx 3D 3M is ideally suited for the design of monolithic microwave integrated circuits (MMICs), radio-frequency integrated circuits (RFICs), low-temperature co-fired ceramic (LTCC) circuits, high-temperature superconducting (HTS) circuits, radio-frequency identification (RFID) antennas, patch antennas, slot antennas, wire antennas, and most other RF and wireless antennas.
- HyperLynx 3D EM SI's full-wave 3D EM design and verification solution meets the capacity and run-time performance demands of complete package, PCB or circuit-level simulation. Importing Allegro Package Designer and GDSII format design data is supported.
Full Custom Design
- Analog Mixed-Signal AMS simulator package provides designers with a number of software tools that are used for verifying complex digital, analog and mixed-signal System-on-Chip (SoC) designs. It is a comprehensive language-neutral tool with functionality for multi-discipline design flows enabling top-down design and bottom-up verification of multi-million gate analog/mixed-signal System-on-Chip designs. Integrated into the Mentor Graphics IC flow and Cadence Analog Design Environment (ADE), it has complete language support which includes VHDL, Verilog, SystemC, VHDL-AMS, Verilog-AMS, SPICE, and C. Key functionality Includes:
- Eldo Classic – The Mentor Graphics “Golden” spice circuit simulator
- Eldo Premier – A faster version of Eldo with support for multiple cores, giving increased performance and capacity, without compromising accuracy.
- Eldo-RF – Extends the capabilities of Eldo to offer RF specific analyses, including; steady state, steady-state small-signal, steady state noise, and oscillator and phase noise. It also included a range of RF specific measurements.
- EZWave – A graphical waveform analysis environment with a graphical waveform calculator and parametric analyser. It can plot time or frequency domain waveforms of any type: analog, digital, eye diagram, smith chart, polar or complex chart, and histogram.
- Questa ADMS and Questa ADMS RF – A unified mixed-signal simulation and analysis environment, integrates Eldo, Eldo-RF, Questa and EZWave, and provides an integrated graphical debug and analysis environment.
- Pyxis is a new Custom IC design platform including integrated design solutions for; design capture, floorplanning, custom routing, polygon editing, physical layout, schematic-driven layout, electrical rule checking for Pyxis schematics, and chip assembly. This functionality is provided by three main component tools: Pyxis Schematic, which provides schematic capture, simulation control, and results viewing; Pyxis Layout Suite, which provides physical implementation, schematic driven layout, interactive sign-off verification and chip assembly.
The Calibre tools are a comprehensive range of physical verification tools, including; DRC, ERC, LVS, RCX, and DFM analysis. The tools integrate closely into a range of third party design environments, as well as a range of products from Mentor including; Calibre DesignRev , IC Flow and Pyxis.
- Calibre nmDRC is the industry standard signoff layout “Design Rule Checking” tool. It reads the GDSII, OASIS, LEF/DEF file formats and directly reads both OpenAccess and Milkyway database formats. It is fully multi-CPU enabled to speed up the physical verification tasks. It also integrates with a range of layout environments for interactive DRC debug, including; DesignRev, IC Flow, Pyxis, Cadence Virtuoso, Cadence Encounter, and Synopsys IC Compiler.
- Calibre nmLVS is a high speed LVS (and ERC) checking tool. It can be run flat, or preferably in hierarchical mode to speed runtimes. It integrates tightly with Calibre RVE to facilitate rapid LVS debug, and cross-probing between the schematic environment and the layout environment. It integrates with a range of full-custom design environments for interactive LVS debug, including; IC Flow, Pyxis, and Cadence Virtuoso.
- Calibre xRC, Calibre xL, Calibre xACT 3D provide detailed RLC extraction for analogue and digital designs. Calibre xRC provides high capacity full chip RC extraction, with the option for loop inductance and resistance extraction with the Calibre xL option. Whilst for small geometry processes, the Calibre xACT 3D provides high accuracy parasitic extraction (using a fast 3D field solver) for transistor level (device and interconnect) parasitic extraction, and is especially suited for sensitive analogue circuits, RF circuits and 3D IC TSVs.
- Calibre Interactive is a DRC/LVS/xRC setup and invocation environment which is integrated with a wide range of digital standard cell layout and full-custom layout tools.
- Calibre RVE is a graphical debugging and reviewing environment for rapid analysis and guidance on layout errors. It is used with Calibre DRC/ERC, LVS, PERC or xRC and integrates with a wide range of digital standard cell layout and full-custom layout tools.
- Calibre DesignREV is a chip assembly and integration tool which enables rapid GDSII/OASIS design import, visualization, editing and GDSII/OASIS export. It handles very large designs rapidly and efficiently, and integrates with other Calibre tools, including; DRC and DFM. It support scripting to perform repeatable design assembly tasks.
- Calibre PERC is a programmable electrical rule checker, which can be used to check layouts for a range of electrical issues, specifically including; ESD (Electrostatic Discharge) checks and Multi-Voltage power domain checks. Included with Calibre PERC, is the PERC Catalog, which includes a range of common PERC verification examples for Advanced ERC (AERC) checks and for ESD checks.
- Calibre 3DSTACK enhances the Calibre DRC and LVS engines to support 3D (and 2.5D) IC physical verification. It enables designers to define how multiple dies are stacked together as a 3D IC or as a 2.5D IC using a silicon interposer (by defining the layer stack in its 3D-IC Description Language). The layer stack can then be verified, checking the TSVs, and bump bonds to ensure correct alignment and electrical connectivity between the die.
- Calibre RealTime provides interactive layout DRC (as you edit) capabilities, which integrates into the Pyxis full custom layout environment. It enables Design Rule Driven (DRD) layout editing within the Pyxis environment, by running fast incremental DRC of the edited area to give nearly instantaneous feedback on design rule violations. Critically it is using the standard Calibre DRC rule decks to ensure that designers have no surprises when they do the full-chip/block DRC.
- Calibre LFD is used to apply lithographic process simulation to drawn layouts to identify lithographic hotspots. These “hot spots”, structures with a higher probability of failing due to litho process variations can be identified and graded to determine which have the highest potential for yield improvement.
- Calibre CMPAnalyzer is use to simulate Chemical Mechanical Polishing (CMP) induced thickness variations for a particular layout, in order to assess planarization of the layout. This can be used to optimise the layout in YieldEnhancer, or be fed into Calibre xRC to produce optimised RC extraction results which account for thickness variation.
- Calibre YieldAnalyzer runs Critical Area Analysis (CAA) and Critical Feature Analysis (CFA) on your design, to quantify design sensitivity to a particle defects (from foundry defect density distributions for each layer) and systematic issues (represented by adherence to a recommended design rules). For CAA Calibre YieldAnalyzer is used to generate random defect hotspot maps for your design, whilst for CFA it produces a weighted score for each recommended rule violation.
- Calibre YieldEnhancer is used to perform automated optimisation of your design, based on CAA and CFA information from Calibre YieldAnalyzer
Fixing operations include; 1) single via additions, 2) replacement of a single via with two symmetrically placed vias, 3) edge modifications based on multi-layer checks (such as enclosure and extensions rules), 4) single layer grow operations, and 5) Smart Fill (for CMP planarity optimisation).
- SystemVision is a multi-domain (Mechatronic) system modelling environment. It enables the design and simulation of complex systems in a single simulation and analysis environment. It supports the modelling and co-simulation of a wide range of different electrical and mechanical scenarios including; analogue/digital circuits; thermal, mechanical and hydraulic systems; continuous and sampled-data control systems. It supports co-simulation with a range of languages including; VHDL-AMS, Spice and C code.
- Vista is a SystemC Transaction Level Modelling (TLM 2.0) environment for rapid exploration of system architecture and performance, including examining hardware/software tradeoffs. It includes the following capabilities; rapid system assembly, advanced SystemC/TLM debug capabilities , architecture exploration, and detailed assessment of performance and power under user defined load scenarios. Additionally Vista Model Builder provides the capability to quickly generate detailed SystemC TLM models from either a C model or from detailed RTL. Functionality and interface characteristics can be automatically extracted from the C model or from RTL code, whilst timing and power characteristics can be generated by either estimation (for the C models) or by automated extraction (for RTL models).
- FormalPro is a formal equivalence checking tool, which compares two different representations of a digital designs to confirm that they implement the same functionality. It is a critical step used during the digital design flows to verify that the final gate-level netlist has the same functionality as the original RTL model (“RTL to Netlist” and “Netlist to Netlist”). i.e. to ensure that the synthesis and place and route tools have not introduced errors in the design. It offers full support for both ASIC (Digital IC) design flows and for FPGA (Xilinx, Altera and Actel) design flows. For ASIC flows it also support low power verification using UPF. It is also used to compare VHDL vs Verilog (RTL-vs-RTL), when validating code translation from VHDL to Verilog or vice versa.
- The Tessent tool suite comprises of a wide range of tools for Digital IC test insertion and ATPG. Tools include;
• Tessent DFT Advisor - scan test insertion for ASIC designs
• Tessent TestKompress - compressed scan test capabilities for ASIC designs
• Tessent BoundaryScan - boundary scan insertion for ASIC designs
• Tessent FastScan - Automatic Test Pattern Generation (ATPG)
• Tessent MemoryBIST - memory BIST (Build In Self Test) insertion for ASIC designs
• Tessent Diagnosis – test diagnostics to diagnose failing ATE test patterns
• Tessent IJTAG – automated support for implementing the IEEE P1687 standard
- Visual Elite is a design environment for Verilog/VHDL/SystemC code development, exploration and refinement. It is especially suited for rapid design development, by using a wide variety of textual and graphical design entry techniques. It supports a mixture of TLM and RTL modelling levels to facilitate rapid exploration and refinement of designs. For simulation, it links into Questa and for TLM model development it links into Vista.
Advanced Digital Functional Verification
- Questa Formal is a high capacity formal proof engine, which is enables designers to exhaustively verify properties of designs. It applies a wide range of proof engines to exhaustively verify user defined SVA or PSL assertions/properties. It can also generate and prove a range of automatically extracted properties (Questa AutoCheck) for common design issues including; arithmetic overflows, multiply driven busses/nets and X generation checks.
- Questa Verification IP Is a library of verification components for verifying the compliance of a design to a range of supported protocols. These can be used for both simulation (e.g. using Questa SV AFV) and formal verification (e.g. using Questa CDC/Formal).
Schematic Design, Full forward and backward annotation to PCB layout through the design capture tools supporting hierarchical support, design rule constraints and component management.
Component management, available through single spreadsheet, multiple libraries are managed in Access or Excel databases and kept in-sync and up-to-date to avoid problems later in the design cycle. PADS
connects to the website PartQuest and is tightly integrated to the component supplier Digi-Key and their full component catalog.
Simulation and Analysis, board level analog simulation is integrated directly into the schematic environment and includes DC, frequency, and time-domain analysis, as well as statistical approaches, such as Monte Carlo Analysis
and multiple sweep analyses.
Thermal analysis, is available to the layout as soon as placement is complete, allowing you early analysis of temperature profiles, gradients, and isothermal maps, allowing you to make changes to any potential hot spots.
Layout, placement and visualisation in 3D identifies conflicts early to ensure trouble free assembly. After routing the critical nets, based on design rules, can be analysed for signal integrity to ensure design criteria continues to be met. Autorouters include fanout and routing by individual components or groups of components. Auto-dimensioning, direct DXF import into the board and part library editor, advanced fabrication verification tools, assembly variant functions, and 3D viewing and editing are also included.
HyperLynx Analog, SI, PI, DRC, Full-Wave Solver, and 3D Solver analysis tools are all included in the PADS bundle.
Catapult High Level Synthesis reduces design time and verification effort by enabling hardware designers to use untimed C/C++ or SystemC for ASIC and FPGA design entry.
No timing or micro-architectural information is required in the source code, these are both automatically added (guided by user constraints) during the synthesis process. This user guided methodology enables designers to quickly evaluate different micro-architecture solutions, exploring the performance / area trade-offs to find the best solutions, all without modification to the C++ / SystemC source code.
For C++ designs, the top level hardware interfaces (data input and output interfaces) are inserted automatically using interface synthesis, guided by constraints. For more complex designs, Catapult supports SystemC which enables designers to explicitly specify the top level (and block level) interface protocols and cycle timing in the SystemC code. SystemC based design also enables designers to explicitly specify design hierarchy, which is required for multi-clock systems and for larger designs.
Catapult also provides an automated verification flow, which allows the generated RTL to be verified using the original C++ or SystemC testbench. Simulation of the Catapult generated RTL can be carried out against the original untimed C++ or original SystemC designs. This eliminates the need to write pin-level interfacing and bit-timed RTL environments to verify the RTL blocks created by Catapult before moving to system integration.
Key features include:
- C / C++ / SystemC synthesis
- Faster, efficient hardware design compared with hand-coded methodologies
- Micro-architectural constraints enable predictable synthesis results
- Automatic interface synthesis for C / C++ designs (controlled using constraints)
- Control over implementation and latency/area/throughput results enabled by an incremental refinement methodology
- Automated RTL verification using original untimed C++ testbench
- Outputs: RTL VHDL & Verilog
* Please note: That the Catapult licenses available to academia are the Catapult University Version (Catapult UV) which is a subset of the Catapult SL version. Catapult UV doesn’t include certain features such as Hierarchical C++ Synthesis or the low power optimisations; however it does include full hierarchical SystemC synthesis.
Click on a product name to view the datasheet
|T-Spice||Circuit level simulator|
|Tanner Waveform||Waveform viewer|
|L-Edit *||Full custom layout editor|
|SPR||Legacy standard cell place and route|
|Standard DRC||On-line geometric design rule checker|
|Interactive DRC||Real-time DRC violation checker|
|Standard Extract||Device level extractor to SPICE netlist|
|Standard LVS||Layout Versus Schematic comparison and diagnostics|
|Cross Sectional Viewer||Layout cross section to show circuit in fabrication stages|
|UPI||User programmable interface / macro generator|
|SDL||Netlist to layout generator|
|SDL Router||Automatic routing engine|
|DevGen Standard||Parameterized device generator|
|Node Highlighting||Connection visualization|
|Curve Tools||Chamfers and fillets generator for all-angle objects|
|Pad Cross-Reference Extractor||
Extractor for Pad location from layout
|Tanner Verify||DRC and EXT using foundry Calibre/Dracula rulesets|
|Utilities||Licensing and installation utilities and diagnostics, and troubleshooting documentation|
* Please note: L-Edit is only available as part of this bundle and is not available separately as a standalone product.
Tanner Suite Licenses
Please note: All new (or re-hosted) Europractice Tanner licenses are now generated using the Mentor Graphics FlexNet network licensing. This is the same network license daemon as is used by the other Mentor Graphics tools. The Mentor Graphics FlexNet license daemon supports both Windows and Linux for the license server OS. Note: It is no longer possible to get SentinelLM (Net-ID) based license files. New Tanner Mentor Graphics daemon licenses will work with the following specific tool releases which are available on our FTP server:
• 2015.4-u1 – Supporting both Windows and Linux (Equivalent to the 16.34 Net-ID based Tanner release)
• 16.26 – Supporting only windows (Equivalent to the 16.25 Net-ID based Tanner release)
• 16.13 – Supporting only windows (Equivalent to the 16.12 Net-ID based Tanner release)
• 15.24 – Supporting only windows (Equivalent to the 15.23 Net-ID based Tanner release)
|Last modified: February 8, 2018|