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FPGA and Board Design (FPGA)

FPGA and Board Design flow comprises of the following environment flows;

Digital Design & Verification

FPGA Synthesis

PCB Design tools & Verification

Advanced Digital Functional Verification


Full Suite (Full)

The Full Suite flow comprises a number of different environment flows and includes the FPGA & Board Design tools, described in the above section;

HYperLynx 3D EM Field Solver

Full Custom Design

Physical Verification

Advanced Tools

DFM Tools

System Modelling

Digital Implementation

Advanced Digital Functional Verification


PADS PCB

PADS PCB

Schematic Design, Full forward and backward annotation to PCB layout through the design capture tools supporting hierarchical support, design rule constraints and component management.

Component management, available through single spreadsheet, multiple libraries are managed in Access or Excel databases and kept in-sync and up-to-date to avoid problems later in the design cycle. PADS connects to the website PartQuest and is tightly integrated to the component supplier Digi-Key and their full component catalog.

Simulation and Analysis, board level analog simulation is integrated directly into the schematic environment and includes DC, frequency, and time-domain analysis, as well as statistical approaches, such as Monte Carlo Analysis and multiple sweep analyses.

Thermal analysis, is available to the layout as soon as placement is complete, allowing you early analysis of temperature profiles, gradients, and isothermal maps, allowing you to make changes to any potential hot spots.

Layout, placement and visualisation in 3D identifies conflicts early to ensure trouble free assembly. After routing the critical nets, based on design rules, can be analysed for signal integrity to ensure design criteria continues to be met. Autorouters include fanout and routing by individual components or groups of components. Auto-dimensioning, direct DXF import into the board and part library editor, advanced fabrication verification tools, assembly variant functions, and 3D viewing and editing are also included.

HyperLynx Analog, SI, PI, DRC, Full-Wave Solver, and 3D Solver analysis tools are all included in the PADS bundle.


Catapult HLS

Catapult High Level Synthesis reduces design time and verification effort by enabling hardware designers to use untimed C/C++ or SystemC for ASIC and FPGA design entry.
No timing or micro-architectural information is required in the source code, these are both automatically added (guided by user constraints) during the synthesis process. This user guided methodology enables designers to quickly evaluate different micro-architecture solutions, exploring the performance / area trade-offs to find the best solutions, all without modification to the C++ / SystemC source code.


For C++ designs, the top level hardware interfaces (data input and output interfaces) are inserted automatically using interface synthesis, guided by constraints. For more complex designs, Catapult supports SystemC which enables designers to explicitly specify the top level (and block level) interface protocols and cycle timing in the SystemC code. SystemC based design also enables designers to explicitly specify design hierarchy, which is required for multi-clock systems and for larger designs.
Catapult also provides an automated verification flow, which allows the generated RTL to be verified using the original C++ or SystemC testbench. Simulation of the Catapult generated RTL can be carried out against the original untimed C++ or original SystemC designs. This eliminates the need to write pin-level interfacing and bit-timed RTL environments to verify the RTL blocks created by Catapult before moving to system integration.

Key features include:

* Please note: That the Catapult licenses available to academia are the Catapult University Version (Catapult UV) which is a subset of the Catapult SL version. Catapult UV doesn’t include certain features such as Hierarchical C++ Synthesis or the low power optimisations; however it does include full hierarchical SystemC synthesis.


Tanner Suite

The Tanner Suite from Mentor Graphics is a complete suite of tools for analogue IC design, including; schematic capture, circuit simulation, and waveform probing to physical layout and verification.

Tanner Suite
Click on a product name to view the datasheet
Product Function
S-Edit Schematic Capture
T-Spice Circuit level simulator
Tanner Waveform Waveform viewer
L-Edit * Full custom layout editor
SPR Legacy standard cell place and route
Standard DRC On-line geometric design rule checker
Interactive DRC Real-time DRC violation checker
Standard Extract Device level extractor to SPICE netlist
Standard LVS Layout Versus Schematic comparison and diagnostics
Cross Sectional Viewer Layout cross section to show circuit in fabrication stages
UPI User programmable interface / macro generator
SDL Netlist to layout generator
SDL Router Automatic routing engine
DevGen Standard Parameterized device generator
Node Highlighting Connection visualization
Curve Tools Chamfers and fillets generator for all-angle objects
Pad Cross-Reference Extractor

Extractor for Pad location from layout

Tanner Verify DRC and EXT using foundry Calibre/Dracula rulesets
Utilities Licensing and installation utilities and diagnostics, and troubleshooting documentation

* Please note: L-Edit is only available as part of this bundle and is not available separately as a standalone product.

Tanner Suite Licenses

Please note: All new (or re-hosted) Europractice Tanner licenses are now generated using the Mentor Graphics FlexNet network licensing. This is the same network license daemon as is used by the other Mentor Graphics tools. The Mentor Graphics FlexNet license daemon supports both Windows and Linux for the license server OS. Note: It is no longer possible to get SentinelLM (Net-ID) based license files. New Tanner Mentor Graphics daemon licenses will work with the following specific tool releases which are available on our FTP server:


• 2015.4-u1 – Supporting both Windows and Linux (Equivalent to the 16.34 Net-ID based Tanner release)
• 16.26 – Supporting only windows (Equivalent to the 16.25 Net-ID based Tanner release)
• 16.13 – Supporting only windows (Equivalent to the 16.12 Net-ID based Tanner release)
• 15.24 – Supporting only windows (Equivalent to the 15.23 Net-ID based Tanner release)

Last modified: February 8, 2018