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Intel is a leading provider of FPGA (Field Programmable Gate Array) devices and provide a comprehensive suite of development tools for FPGA design as well as preconfigured design blocks to enable fast system assembly. Until 2016, the Intel Programmable Solutions Group was known as Altera.

Quartus Prime

Quartus Prime is available in two editions, Standard and Pro. The Standard tools address the current mainstream devices in the four and five series while the Pro edition tools are only currently used for the Arria 10 devices with Stratix 10 to follow. A license for both editions is supplied with each donation. Note that Pro edition and many of the IP blocks have only recently been added and existing licenses do not update automatically. To get access to these new features please submit a new donation form.


Quartus Prime Quartus Prime is a complete FPGA development environment for design entry, simulation, synthesis, place and route and verification of Intel FPGA designs. Quartus includes SOPC Builder, DSP Builder, and Qsys. Licenses for a range of MegaCore IP blocks, including the Nios II soft processor, are included with Quartus.
SOPC Builder SOPC Builder allows design of Intel embedded FPGA systems, based on the Nios II soft processor.
DSP Builder DSP Builder includes a toolbox of DSP IP for use with MATLAB Simulink. DSP Builder generates synthesizable RTL (for Intel FPGA devices). DSP Builder allows use of the Matlab/Simulink framework for design entry, simulation and verification.
Qsys The Qsys System Integration Tool is based on network-on-a-chip (NoC) technology and allows users to efficiently build hierarchical systems by connecting systems and intellectual property (IP) together. Qsys supports industry-standard interfaces including the Avalon and ARM AMBA AXI interfaces, and allows users to mix and match IP cores of different interfaces into their designs.

Intel FPGA licenses will be donated free of charge to Europractice academic sites. There is no cost for licenses, but Intel FPGA maintenance will apply. Sites must be in maintenance, or apply to be at the time of order. See How to Order below for more details.

Intel FPGA annual maintenance per site (independent of number of licenses): €200

Intellectual Property blocks

Pre-characterised design blocks which can be customised. A small set of mostly memory IP is included with the Quartus Prime licenses; the more advanced IP needs to be requested separately. The number of seats of IP will match the number of Quartus Prime requested.

IP Base Suite (Automatically included)
Memory Controller IP and basic filters. Includes: NCO (Numerically Controller Oscillator), FFT (Fast Fourier Transform) Compiler, FIR (Finite Impulse Response) Compiler, QDRII+ SRAM Controller with UniPHY, RLDRAM II Controller with UniPHY, DDR2, DDR3 and LPDDR2 Controllers with UniPHY.

DSP and Embedded MegaCore Bundle
The NIOS softcore processor and some further DSP filters. Note that you must add this bundle to get the NIOS, it is no longer included in the base bundle. Includes: IP-NIOS, IP-CIC (Cascaded Integrator-Comb), IP-RSCODECII, IP-VITERBI/SS, IP-VITERBI/HS and IP-UART-16550.

Protocol MegaCore Bundle
A full set of Ethernet cores at 1G, 10G, 40G and 100G plus Interlaken up to 150G. Note that not all protocols are compatible with all devices. Includes: IP-TRIETHERNETF,IP-RIOPHY,IP-10GETHMACF,IP-XAUIPCS,IP-10GBASERPCS,IP-CPRI,IP-DXAUIPCS,IP-ILKN/100G,IP-100GEMAC,IP-100GEPHY,IP-40GEMAC,IP-40GEPHY,IP-10GBASEKRPHY,IP-RAPIDIOII, IP-SLITE3/ST,IP-ILKN/50G,IP-40GBASEKR4PHY,IP-10GEUMACF,IP-PCIE/8,IP-JESD204B,IP-DP,IP-40GEUMACPHYF,IP-100GEUMACPHYF,IP-HMCSR15FW,IP-ILA/50G,IP-ILA/100G,IP-ILA/200G,IP-CPRI-V6,IP-10GEUMAC,and IP-HDMI.

Video and Image Processing IP Bundle
A full set of video processing IP. Includes: Chroma Resampler, Gamma Corrector II, 2D FIR Filter, Alpha Blending Mixer, Deinterlacer, Frame Buffer, Clocked Video to Image Stream Convertor, Image Stream to Clocked Video Convertor, Color Plane Sequencer II, VIP Control Synchronizer, Avalon-ST Video Monitor, Interlacer II, Scaler II, VIP Trace System, Deinterlacer II, VIP Frame Reader, VIP Clipper II , VIP Clocked Video Output II, VIP Clocked Video Input II, VIP Color Space Converter II, VIP Test Pattern Generator II, VIP Switch II, VIP Frame Buffer II, VIP Mixer II, VIP Chroma Resampler II, VIP 2D FIR Filter II, VIP Avalon-ST Video Stream Cleaner. Plus SDI/SDI II and DisplayPort.


DE2-115 Development Board


The DE2-115 development board is the third generation of the popular DE2 boards, and includes a Cyclone IV EP4CE115.

The EP4CE115 with 114,480 logic elements (LEs) is the largest in the Cyclone IV E series. The EP4CE115 offers up to 3.9-Mbits of RAM, 266 multipliers and a High-Speed Mezzanine Card (HSMC) connector. The HSMC supports additional functionality via HSMC daughter cards and allows direct connection between two or more FPGA-based boards for large-scale prototype development.
The DE2 kit includes a DE2-115 board, start-up guide/CD, power adapter, USB cable, and a remote control.

Further information can be found here: DE2-115 User Manual


SoCKit Development Board


The SoCKit development board uses the Cyclone V SoC FPGA. In addition to the 110,000 Logic Elements (roughly equivalent to the modern DE2 board), the Cyclone V SX SoC features a full ARM-based hard processor system (HPS) with dual core Cortex-A9 processors at 800 MHz 512KB L2 Cache and a multiport SDRAM controller. The board itself features 2GB of DDR3 SDRAM, 128MB QSPI Flash, Gigabit Ethernet, USB, VGA, a small LCD panel, and the usual host of buttons switches and LEDs. The board also offers an HMSC connector compatible with DE2 daughterboards.

The package includes the SoCKit Board, SoCKit Quick Start Guide, Power DC Adapter (12V), a Ethernet Cat 5e Cable and Type A to Micro B USB Cable x2.

Further information can be found here: SoCKit User Manual


DE4-230/DE4-530 Development Board


The DE4 Development board is a high performance development platform with two variants; one based on the Stratix IV 4SGX230 FPGA with 228,000 Logic Elements (DE4-230), and the other based on the Stratix IV EP4SGX530 FPGA with 531,200 Logic Elements (DE4-530). The DE4 includes 2xDDR2 SO-DIMM sockets, SD card socket, SMA, SATA, Gigabit Ethernet, PCIe x8 and an array of pushbuttons, switches and LEDs.

Two HSMC interfaces are available, allowing multiple DE4 boards to be stacked together offering capability for large-scale ASIC prototyping.
The DE4 kit includes the board, start-up guide/DVD, power adapter, DDR2-800 1GB SO-DIMM; HSMC debug board, loopback adaptor and height extension card (Male-to-Female); PCIe bracket and power cable, Ethernet/Sata cables.

Further information can be found here: DE4 User Manual

DE5a-Net-DDR4 Development Board


The DE5a-Net-DDR4 is a high performance board built around an Arria 10 FPGA; it is particularly suited to ultra-low latency comms projects or any project requiring a large capacity device. The device is an Arria 10 GX FPGA (10AX115N2F45E1SG) and the board has 256MB Flash, four QDRII+ SRMAS and DDR3 SODIMM Slots each capable of housing 8GB SODIMMs at 1200 MHz. There are four QSFP+ connectors plus SMA clock input and clock output.

Further information can be found here: DE5a-Net-DDR4 User Manual

Note that to use the Arria 10 family you will need to use the Quartus Prime Pro product. If your current licenses do not support Quartus Prime Pro then please submit a new donation form for replacement licenses.

For further information on hardware, please contact the Microelectronics Support Centre

Please note that STFC aims to maintain a small stock of these boards for shipment on receipt of order. Sites ordering these boards should receive them ahead of any software being ordered, which will be batched up into the next monthly order in the normal manner.

Operating Systems

Intel FPGA Quartus Prime

How to Order

Detailed instructions on how to place an order are given in our Order Procedures. Intel FPGA orders are not subject to the 25th day of the month order deadline that most other Europractice orders are.





PLEASE ENSURE that you read the End User Agreement Notes before downloading the End User Agreements

Last modified: July 26, 2018