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Fully synthesisable MIPS Warrior M-Class CPUs

Two, fully synthesisable, MIPS Warrior M-Class CPUs are available the M5100 and M5150.

The M51xx cores are a 32-bit Series 5 architecture MIPS processor core and made available as fully configurable/synthesizable RTL code. Both cores offer a 5-stage pipeline with 32-bit address and data paths, supporting the MIPS32 Instruction set, MIPS32 Enhanced Architecture Features and the microMIPS Instruction Set Architecture with optimized MIPS32 16-bit and 32-bit instructions.

Both cores are supplied as non-obfuscated RTL which can be synthesised to a range of suitable ASIC technologies and incorporates extensive fine-grain clock gating for configurable power management and low power applications. The M5100 offers integrated SRAM controller and real time execution unit and ideal for small footprint, low power microcontroller applications. The M5150 additionally incorporates a high performance L1 cache controller and virtual memory management support for high performance embedded system applications. A number of optional features and interfaces can be included or omitted during the configuration/synthesis process. A Bus Interface Unit offers an AMBA 3 AHB interface.


MIPS M5100 architecture MIPS M5150 architecture


M51xx Highlights

Architecture
MIPS32 Release 5 Architecture
microMIPS ISA Enhanced code compression ISA of combined 16- and 32-bit instructions
Supports all existing MIPS32 instructions; adds new 16- and 32-bit instructions
Hardware Virtualization
Create multiple execution environments isolated from each other, operating at kernel privilege level with Hypervisor/Secure Monitor (Root) manages access rights for each Guest
Supports multiple Memory Management Unit options for optimum area vs. functionality
Allows sharing of resources (memory, DSP, FPU etc.) between Guests
DSP Module r2
Dedicated pipeline, operates in parallel with core integer pipeline
Implements over 150 instructions, including 70 SIMD and 38 Multiply/MAC instructions
Enhanced Multiply & Divide Unit
Supports up to 4 Accumulators
Floating Point Unit (FPU)
Single and double precision IEEE 754 compliant FPU
Supports IEEE-754 2008 Nan and ABS instructions
Dedicated 7-stage pipeline, operating in parallel with core integer pipeline
Most instructions execute with 1 cycle throughput and 4 cycle latency
Executes 1:1 Core:FPU clock ratio
Supports both MIPS32 and microMIPS instructions
Anti-Tamper
Injection of random pipeline stalls
Cache/SPRAM address and data scrambling
2 pseudo random number generators for use by the user software and core logic
Memory Controller
M5150 L1 cache controller for Instruction and Data sizes up to 64KB, 4-way set associative
M5100 32-bit address and data SRAM interface, separate or unified instruction and data interface
Bus Interface Unit
AMBA 3 AHB
EJTAG Debug & Trace
Secure debug feature prevents streaming instructions through the EJTAG port
Supports enhanced iFlowtrace with additional event trace modes
Simple/Complex instruction and data breakpoint support 2I/1D, 4I/2D, 6I/2D, 8I/4D
Support for 2 Performance Counters with multiple event type options
Instruction and data address sampling: zero overhead, qualified read/write
Support for 2-wire cJTAG debug interface
Power Management
Incorporates extensive fine-grain clock gating
Implements a Power Down mode initiated by a WAIT instruction


The MIPS M5100 and the M5150 are available to Europractice members and supplied as non-obfuscated RTL. Each core also includes access to 5 x VMC Licenses for Instruction Accurate simulation and HDL co-simulation. VMC is licensed by a run-time license mechanism based on FLEXnet(FLEXlm) software license manager, with the license server hosted by Europractice at STFC Rutherford Appleton Laboratory. Authorised users of MIPS M5100 or M5150 within Europractice members will have a local installation of VMC but the license server will be provided and maintained by Europractice with users obtaining licenses at run-time across the network from the Europractice License server using the port@host mechanism. Consequently, Europractice members will require a continuous network connection to the license server in order to run VMC. Local license servers based within Europractice member institutions are not available for VMC.



How to Order

Orders are placed with the vendor on a single order, once per month. To be included in the current month's order, all documents including original ink-signed paper End User Agreements (if applicable) must be received by the Microelectronics Support Centre no later than the 25th day of the month.

Detailed instructions on how to place an order are given in our Order Procedures.

MANDATORY DOCUMENTS FOR ALL ORDERS

MANDATORY DOCUMENTS FOR FIRST TIME ORDER FROM THIS VENDOR ONLY

STATEMENT FROM RESEARCH LABORATORIES

PLEASE ENSURE that you read the End User Agreement Notes before downloading the End User Agreements



STFC Home page Europractice membership and design tools access is managed by STFC at the Microelectronics Support Centre, Rutherford Appleton Laboratory, UK. You can contact the Microelectronics Support Centre by email: MicroelectronicsCentre@stfc.ac.uk

Last modified: September 18, 2017