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IC Package

The IC package includes a wide range of tools for digital, analogue and mixed signal design and implementation.

For analogue and mixed-signal designers, this package includes tools for: Spice/fast-spice/mixed-signal simulation (Spice, Verilog-A/AMS, VHDL-AMS), Spice RF analysis, Schematic capture, Simulation management (including montecarlo analysis), custom characterisation environment, circuit optimisation, yield optimisation, parametric sensitivity analysis, Layout editing, Schematic driven layout (constraint aware), Complex device module generators (MODGENs), Full custom floorplanning , Cell/block placer, Layout migration, Cell/chip routing, Interactive DRC, Extraction (RCLK), LVS, DRC, Electromigration analysis, IR Drop analysis, as well as support for multiple design database formats (CDB and OpenAccess).

For digital designers this package includes tools for: logic simulation (covering VHDL, Verilog, SystemC, SystemVerilog, SVA, PSL and e), formal property proof, verification planning and management (and Verification IP), SDC checking and exception generation, CDC checking, RTL (Verilog, SystemVerilog and VHDL) synthesis, high level (C/C++/SystemC) synthesis, test insertion, Physical implementation (Placement, CTS, Routing, and Optimisation), logical quivalence checking, RC extraction, DRC, LVS, signoff timing analysis, signoff power analysis, standard cell library characterisation/re-characterisation, and ATPG.

Product list

IC Package
2017/2018
Release Name Key Tools Supported Platforms*
Linux
(lnx86)
Analog/Full Custom
Design Tools
Virtuoso®
Custom Design Platform
IC 6.1.7 (OA)
Schematic Entry & Editing
Testbench, Specification & Results Management
ADE Explorer for single testbench design exploration
ADE Assembler for multi-testbench for specification-driven design
ADE Verifier analog verification specification cockpit
Virtuoso Variation Option for advanced statistcal analyses
Analog & Mixed Signal Simulation
Waveform Viewer
Connectivity-Driven Layout Entry & Editing Suite
Constraints-Driven Layout Entry & Editing
Electrically Aware Layout & Editing
Constraint Manager
Power Integrity Tools
RHEL 5, 6, 7
Spectre®
SPECTRE 16.1
Analog Simulators, including Spectre®, Ultrasim, APS and XPS
Spectre RF
RHEL 5, 6, 7
Verification IP Verification IP Catalog
VIPCAT 11.3
Verification IP for a range of protocols for server, networking, and storage interfaces RHEL 5, 6
Logic Design & Functional Verification Incisive® Verification Platform
INCISIVE 15.2
Logic simulation
Formal Verification
Verification Planning & Management
Digital Simulation, verification planning, etc
Functional Safetly Simulator for ISO26262
RHEL 5, 6, 7
Indago Debug Platform
INDAGO 17.04
Debug Analyzer RHEL 5, 6, 7
Digital Design
& Synthesis
Tools
Conformal
Constraint Designer &
Formal Equivalence Checker
CONFRML 17.1
SDC timing constraints and clock specification
Formal Equivalence Checking
Low Power Verification
ECO Verification
RHEL 5, 6, 7
Genus™ Synthesis Solution
GENUS 17.1
(replaces RTL Compiler)
Massively parallel RTL synthesis and physical synthesis
RHEL 5, 6, 7
Joules™ RTL Power Solution
JLS 17.1
Unified power calculator for accurate RTL power and signoff-quality gate power
RHEL 5, 6, 7
Digital
Implementation
Tools

Modus Test Solution
MODUS 17.1
(replaces Encounter Test)

Design For Test
Automated Test Pattern Generation
RHEL 5, 6, 7
Silicon Signoff & Verification

SSV 17.1

Tempus Static Timing Analysis
Voltus Power Rail, IR Drop & Thermal Analysis
RHEL 5, 6
Virtuoso Library Characterisation
Liberate 16.1

(formerly Altos)

Liberate library characterisation

Liberate LV library validation

Library Characterisation

RHEL 5, 6, 7
Innovus™ Implementation System
INNOVUS 17.1
(replaces EDI)
Place & Route / Digital Physical Implementation RHEL 6, 7
Physical Verification Assura®
Physical Verification
ASSURA 4.15
DRC & LVS at >90nm RHEL 5, 6, 7
Physical Verification System
PVS 16.1
DRC & LVS at <90nm
RHEL 6, 7
Quantus™ Extraction
EXT 17.1
Parasitic Extraction & Analysis RHEL 5, 6, 7

For a full list of licensed products in the IC Package, please see here
* For further information on the End of Life schedule for releases marked as 'legacy', please contact MicroelectronicsCentre@stfc.ac.uk

Systems Package

The systems package includes a wide range of tools for PCB design.

This package includes tools for: design entry (schematics, HDLs or spreadsheet), constraint entry and management, digital simulation (VHDL, Verilog), board layout, track routing, analogue/mixed-signal simulation, power integrity analysis, signal integrity analysis, symbol library development and management, and a standard footprint parts library.

Product list

Systems Package
2017/2018
Release Name Key Tools Supported Platforms*
Linux
(lnx86)
Windows
(Server 2008,
Server 2012, 7, 8, 10)
PCB Design System, Package & Board
SPB 17.2
Front End PCB Design with Allegro Design Authoring
FPGA-PCB co-design
AMS Simulation
PCB Layout & Routing
Library & Design Data Management
RHEL 5, 6, 7 yes
Signal & Power Integrity Allegro® Sigrity™
SIGRITY 2017
Power-aware Signal Integrity analysis with PowerSI
PowerSI 3D EM Full-Wave Extraction
DC and thermal analysis for packages and boards with PowerDC
IC package model extraction with XtractIM
RHEL 5, 6, 7 yes
Verification IP Verification IP Catalog
VIPCAT 11.3
Verification IP for a range of protocols for server, networking, and storage interfaces RHEL 5, 6 no
Logic Design & Functional Verification Incisive® Verification Platform
INCISIVE 15.2
Logic simulation
Formal Verification
Verification Planning & Management
Digital Simulation, verification planning, etc
RHEL 5, 6, 7 no

For the full list of licensed products in the Systems Package, please see here

TLM Package

The TLM package includes tools for digital systems design and verification.

This package includes tools for: logic simulation (covering VHDL, Verilog, SystemC, SystemVerilog, SVA, PSL and e), formal property proof, verification planning and management (and Verification IP), SDC checking and exception generation, CDC checking, RTL (Verilog, SystemVerilog and VHDL) synthesis, high level (C/C++/SystemC) synthesis, and logical equivalence checking.

Product list

TLM Package
2017/2018
Release Name Key Tools Supported Platforms*
Linux
(lnx86)
Verification IP Verification IP Catalog
VIPCAT 11.3
Verification IP for a range of protocols for server, networking, and storage interfaces RHEL 5, 6
Logic Design & Functional Verification Incisive® Verification Platform
INCISIVE 15.2
Logic simulation
Formal Verification
Verification Planning & Management
Digital Simulation, verification planning, etc
Tools to create Virtual Platforms using fast processor models, for pre-RTL software development
RHEL 5, 6, 7
Digital Design
& Synthesis
Tools
Conformal
Constraint Designer &
Formal Equivalence Checker
CONFRML 17.1
SDC timing constraints and clock specification
Formal Equivalence Checking
RHEL 5, 6, 7
Genus™ Synthesis Solution
GENUS 17.1
(replaces RTL Compiler)
Massively parallel RTL synthesis and physical synthesis
RHEL 5, 6, 7

For a full list of licensed products in the TLM Package, please see here
* For further information on the End of Life schedule for releases marked as 'legacy', please contact MicroelectronicsCentre@stfc.ac.uk

PCB Studio Package

The PCB studio package provides an alternative PCB design environment, supporting the Microsoft Windows environment.

The package includes tools for: design entry, board layout, routing up to 6 metal layers, spice simulation, and entry level interconnect analysis.

Product list

PCB Studio Package
2017/2018
Release Name Key Tools Supported Platforms*
PCB Design PCB Studio
SPB 17.2
Front End PCB Design with Capture CIS
FPGA System Planner (2 FPGAs)
AMS Simulation
PCB Layout & Routing (up to 6 layers)
Windows (Server 2008, Server 2012, 7, 8, 10)
Signal Integrity Allegro® Sigrity™
SIGRITY 2017
Signal Integrity Analysis Windows (Server 2008, Server 2012, 7, 8, 10)

For a full list of licensed products in the PCB Studio Package, please see here


*For detailed platform support information please contact MicroelectronicsCentre@stfc.ac.uk

Last modified: September 18, 2017